BibTex RIS Kaynak Göster

A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior

Yıl 2013, Cilt: 12 Sayı: 24, 39 - 52, 01.12.2013

Öz

This paper presents a low power, compact VLSI implementation of a silicon neuron based on Izhikevich neuron model and synchronous network behavior of three coupled neurons, operating at biological timescale. The neuron circuit consists of two first order log domain filters, each corresponding to a variable of the neuron model, a positive feedback and resetting circuitry. The filters and as well as the other parts of the design involve source shifted transistors and active diode connections in order to operate at very low current levels yielding low power consumption and large time constants realized with small capacitances. The resetting circuitry contains cascaded simple differential pairs serving as comparators. The inphase and n-phase synchronization behaviors as a possible network dynamics of three coupled neurons are also presented. The coupling is provided by a synapse circuit which is again a first order log domain filter with sigmoid steady state and time constant functions. These sigmoid functions are obtained by using a simple differential pair and translinear loop current multipliers. The log domain design and current-mode operation in a 0.15 µm CMOS process results in low area and sub nano watt power consumption during real time scale operation which makes the circuit suitable for hybrid interface applications or large scale VLSI neuromorphic networks as a hardware simulation tool for computational neuroscience

Kaynakça

  • Bartolozzi, C., Indiveri, G., (2007), "Synaptic dynamics in analog VLSI", Neural Comput., no. 19, pp.2581 -2603.
  • Demirkol, A., Ozoguz, S., (2011), "A low power vlsi implementation of the Izhikevich neuron model," IEEE NEWCAS, pp. 169-172.
  • Demirkol, A., Ozoguz, S., (submitted, 2013), " A Low Power VLSI Implementation of the AdEx Neuron Model with Network Dynamics," submitted to Analog Integrated Circuits and Signal Processing.
  • Izhikevich, E., (2003), “Simple Model of Spiking Neurons,” IEEE Transactions on Neural Networks, vol. 14, no. 6, pp. 1569-1572.
  • in, ., Luj n, M., lana, L. ., avies, S., Temple, S., Furber, S.B., (2010), "Modeling Spiking Neural Networks on SpiNNaker," Computing in Science & Engineering , vol.12, no.5, pp.91,97.
  • Lee, Y., Lee, J., Kim, K., Kim, Y., Ayers, J., (2007), "Low power CMOS electronic central pattern generator design for a biomimetic robot," Neuroncomputing, Vol.71, No. 1-3, pp. 284-296.
  • Linares-Barranco, B., Serrano-Gotarredona, R., Serrano-Gotarredona, C., (2004), “Current Mode Techniques for Sub-pico- mpere Circuit esign,” nalog Integrated Circuits and Signal Processing, vol. 38, pp. 103-119.
  • Livi, P., Indiveri, G., (2009), “ current-mode conductance-based silicon neuron for Address-Event neuromorphic systems,” IEEE ISCAS, pp. 2898-2901.
  • Mead, C., (1989), “Analog VLSI and neural systems” Addison-Wesley.
  • Pinto, R., Varona ., Volkovskii ., Szücs ., (2000), "Synchrononous behavior of two coupled electronic neurons," Physical Review E, vlo.62, pp. 2644-2656.
  • Rangan, V., Ghosh, A., Aparin, V., Cauwenberghs, G., (2010), “ Subthreshold a VLSI Implementation of the Izhikevich Simple Neuron Model,” IEEE EMBC.
  • Schaik, A., Jin, C., McEwan, A., Hamilton, T., (2010), “ Log-domain implementation of the Izhikevich neuron model,” IEEE ISC S, pp. 4253-4256.
  • Schemmel, J., Bruderle, D., Grubl, A., Hock, M., Meier, K., Millner, S., (2010), “A wafer-scale neuromorphic hardware system for large-scale neural modeling,” IEEE ISCAS, pp. 1947-1950.
  • Vogelstein, R., Mallik, U., Culurciello, E., Cauwenberghs, G., Etienne-Cummings, R., (2007), “ multi-chip neuromorphic system for spike-based visual information processing,” Neural Comput., vol. 19, no. 9, pp. 2281–2300.
  • Wijekoon, J., Dudek, P., (2008), “Integrated Circuit Implementation of a Cortical Neuron,” IEEE ISC S, pp. 1784-1787.
  • Wijekoon, J., Dudek, P., (2009), “A CMOS circuit implementation of a spiking neuron with bursting and adaptation on a biological timescale,” IEEE BioC S, pp. 193-196.
  • Yu, T., Cauwenberghs, G., (2010), “Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics” IEEE Transactions on Biomedical Circuits and Systems, 4(3), 139-148.

A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior

Yıl 2013, Cilt: 12 Sayı: 24, 39 - 52, 01.12.2013

Öz

Bu çalışmada, Izhikevich sinir hücresi modelini esas alan düşük güçlü, kompakt ve gerçek zamanlı VLSI bir silikon sinir hücresi gerçeklemesi ile üç hücrenin kuplajından oluşan bir ağın senkron davranışı sunulmuştur. Sinir hücresi devresi, her biri bir değişkene karşılık gelen iki tane birinci derece logaritmik tanım bölgesi filtresinden, pozitif geribesleme ve resetleme alt devrelerinden oluşmaktadır. Filtreler ve diğer devre kısımları, düşük güç tüketimi sağlamak üzere düşük akım seviyelerinde çalışabilmek ve küçük kapasite değerleryle büyük zaman sabitleri elde edebilmek için, ötelenmiş kaynak gerilimli transistörler, aktif diyot bağları içermektedir. Resetleme alt devresi, karşılaştırıcı olarak kaskat bağlanmış basit fark kuvvetlendiricileri içermektedir. Muhtemel bir ağ dinamiği olarak, kuple edilmiş üç nöronun aynıfazlı ve n-fazlı senkronizasyon davranışları da sunulmuştur. Kuplaj, sigmoid sürekli hal ve zaman sabitine sahip bir birinci derece logaritmik tanım bölgesi filtresinden oluşan bir sinaps devresiyle sağlanmıştır. Bu sigmoid fonksiyonlar, basit bir fark kuvvetlendirici ve translinear çevrimli akım çarpıcılar kullanılarak elde edilmiştir. Logaritmik tanım bölgesinde 0.15 µm CMOS parametreli akım modlu bir tasarım, az yer kaplayan, nano watt altı güç tüketen ve gerçek zamanlı çalışan ve bu nedenle hibrit arayüz uygulamalarında ya da hesaplamalı sinir bilimde kullanılabilir büyük ölçekli tümdevre ağ tasarımlarında donanımsal benzetim gereci olarak kullanılabilecek bir tasarım ortaya çıkarmıştır

Kaynakça

  • Bartolozzi, C., Indiveri, G., (2007), "Synaptic dynamics in analog VLSI", Neural Comput., no. 19, pp.2581 -2603.
  • Demirkol, A., Ozoguz, S., (2011), "A low power vlsi implementation of the Izhikevich neuron model," IEEE NEWCAS, pp. 169-172.
  • Demirkol, A., Ozoguz, S., (submitted, 2013), " A Low Power VLSI Implementation of the AdEx Neuron Model with Network Dynamics," submitted to Analog Integrated Circuits and Signal Processing.
  • Izhikevich, E., (2003), “Simple Model of Spiking Neurons,” IEEE Transactions on Neural Networks, vol. 14, no. 6, pp. 1569-1572.
  • in, ., Luj n, M., lana, L. ., avies, S., Temple, S., Furber, S.B., (2010), "Modeling Spiking Neural Networks on SpiNNaker," Computing in Science & Engineering , vol.12, no.5, pp.91,97.
  • Lee, Y., Lee, J., Kim, K., Kim, Y., Ayers, J., (2007), "Low power CMOS electronic central pattern generator design for a biomimetic robot," Neuroncomputing, Vol.71, No. 1-3, pp. 284-296.
  • Linares-Barranco, B., Serrano-Gotarredona, R., Serrano-Gotarredona, C., (2004), “Current Mode Techniques for Sub-pico- mpere Circuit esign,” nalog Integrated Circuits and Signal Processing, vol. 38, pp. 103-119.
  • Livi, P., Indiveri, G., (2009), “ current-mode conductance-based silicon neuron for Address-Event neuromorphic systems,” IEEE ISCAS, pp. 2898-2901.
  • Mead, C., (1989), “Analog VLSI and neural systems” Addison-Wesley.
  • Pinto, R., Varona ., Volkovskii ., Szücs ., (2000), "Synchrononous behavior of two coupled electronic neurons," Physical Review E, vlo.62, pp. 2644-2656.
  • Rangan, V., Ghosh, A., Aparin, V., Cauwenberghs, G., (2010), “ Subthreshold a VLSI Implementation of the Izhikevich Simple Neuron Model,” IEEE EMBC.
  • Schaik, A., Jin, C., McEwan, A., Hamilton, T., (2010), “ Log-domain implementation of the Izhikevich neuron model,” IEEE ISC S, pp. 4253-4256.
  • Schemmel, J., Bruderle, D., Grubl, A., Hock, M., Meier, K., Millner, S., (2010), “A wafer-scale neuromorphic hardware system for large-scale neural modeling,” IEEE ISCAS, pp. 1947-1950.
  • Vogelstein, R., Mallik, U., Culurciello, E., Cauwenberghs, G., Etienne-Cummings, R., (2007), “ multi-chip neuromorphic system for spike-based visual information processing,” Neural Comput., vol. 19, no. 9, pp. 2281–2300.
  • Wijekoon, J., Dudek, P., (2008), “Integrated Circuit Implementation of a Cortical Neuron,” IEEE ISC S, pp. 1784-1787.
  • Wijekoon, J., Dudek, P., (2009), “A CMOS circuit implementation of a spiking neuron with bursting and adaptation on a biological timescale,” IEEE BioC S, pp. 193-196.
  • Yu, T., Cauwenberghs, G., (2010), “Analog VLSI Biophysical Neurons and Synapses With Programmable Membrane Channel Kinetics” IEEE Transactions on Biomedical Circuits and Systems, 4(3), 139-148.
Toplam 17 adet kaynakça vardır.

Ayrıntılar

Birincil Dil Türkçe
Bölüm Araştırma Makaleleri
Yazarlar

Ahmet Şamil Demırkol Bu kişi benim

Serdar Özoğuz Bu kişi benim

Yayımlanma Tarihi 1 Aralık 2013
Gönderilme Tarihi 10 Ağustos 2015
Yayımlandığı Sayı Yıl 2013 Cilt: 12 Sayı: 24

Kaynak Göster

APA Demırkol, A. Ş., & Özoğuz, S. (2013). A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi, 12(24), 39-52.
AMA Demırkol AŞ, Özoğuz S. A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi. Aralık 2013;12(24):39-52.
Chicago Demırkol, Ahmet Şamil, ve Serdar Özoğuz. “A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior”. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi 12, sy. 24 (Aralık 2013): 39-52.
EndNote Demırkol AŞ, Özoğuz S (01 Aralık 2013) A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi 12 24 39–52.
IEEE A. Ş. Demırkol ve S. Özoğuz, “A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior”, İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi, c. 12, sy. 24, ss. 39–52, 2013.
ISNAD Demırkol, Ahmet Şamil - Özoğuz, Serdar. “A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior”. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi 12/24 (Aralık 2013), 39-52.
JAMA Demırkol AŞ, Özoğuz S. A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi. 2013;12:39–52.
MLA Demırkol, Ahmet Şamil ve Serdar Özoğuz. “A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior”. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi, c. 12, sy. 24, 2013, ss. 39-52.
Vancouver Demırkol AŞ, Özoğuz S. A Low Power Real Time Izhikevich Neuron With Synchronous Network Behavior. İstanbul Ticaret Üniversitesi Fen Bilimleri Dergisi. 2013;12(24):39-52.