@article{article_116717, title={A PERFORMANCE ANALYSIS OF CLASSIFIED BINARY ADDER ARCHITECTURES AND THE VHDL SIMULATIONS}, journal={IU-Journal of Electrical & Electronics Engineering}, volume={4}, pages={1025–1030}, year={2011}, author={Sertbaş, Ahmet and Özbey, R.selami}, abstract={In this paper, the  four  binary  adder architectures belong to a different adder class are studied  and  compared with each other  to analyse their performances.  Comparisons include the unit-gate models for area and  delay. As the performance measure, the product of  the area and the delay is used.  By a VHDL simulator, the adder structures are simulated to verify the functional correctness and  to measure delay times}, number={1}, publisher={İstanbul University-Cerrahpasa}