TY  - JOUR
T1  - COMPLEMENTARY PASS TRANSISTOR LOGIC SYNTHESIS WITH 123 DECISION DIAGRAM
AU  - Avcı, Mutlu
AU  - Yıldırım, Tülay
PY  - 2011
DA  - December
JF  - IU-Journal of Electrical & Electronics Engineering
PB  - İstanbul University-Cerrahpasa
WT  - DergiPark
SN  - 1303-0914
SP  - 1045
EP  - 1049
VL  - 4
IS  - 1
LA  - en
AB  - 123 decision diagram is a very effective PTL synthesis tool based on binary decision diagram. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. In this paper the 123 decision diagram is applied to realize CMOS pass transistor logic circuits without restoring buffers. Cell circuits for the 4 bit adder is realized with the CMOS pass transistors using the 123 decision diagram and 4 bit adder is completed by combining the cells.
UR  - https://dergipark.org.tr/en/pub/iujeee/issue//116719
L1  - https://dergipark.org.tr/en/download/article-file/98970
ER  -