TY - JOUR TT - The impact transconductance parameter and threshold voltage of MOSFET’s in static characteristics of CMOS inverter AU - Zabeli, Milaim AU - Caka, Nebi AU - Limani, Myzafere AU - Kabashi, Qamil PY - 2017 DA - October DO - 10.28978/nesciences.358859 JF - Natural and Engineering Sciences JO - NESciences PB - Cemal TURAN WT - DergiPark SN - 2458-8989 SP - 135 EP - 148 VL - 2 IS - 3 KW - CMOS inverter KW - threshold voltage KW - voltage critical value KW - noise margins KW - transconductance parameter N2 - The objective of this paper is to research the impact of electrical and physical parameters thatcharacterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOSinverter for static mode of operation. In addition to this, the paper also aims at exploring thedirectives that are to be followed during the design phase of the CMOS inverters that enabledesigners to design the CMOS inverters with the best possible performance, depending onoperation conditions. The CMOS inverter designed with the best possible features also enables thedesigning of the CMOS logic circuits with the best possible performance, according to theoperation conditions and designers’ requirements. CR - Baker, R. J. (2010). CMOS Circuit Design, Layout and Simulation (3rd ed.). New Jersey, USA: John Wiley & Songs. Caka, N., Zabeli, M., Limani, M., & Kabashi, Q. (2010). Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design. WSEAS Transactions on Circuits and Systems, 8, 557-566. CR - Chang, C. H., Liu, C. O., Zhang, L., & Kong, Z. H. (2016). Sizing of SRAM cell with voltage biasing techniques for reliability enhancement of memory and PUF functions. Journal of Low Power Electronics and Applications, 6, 1-16. Kang, S., & Leblebici, Y. (2016). CMOS Digital Integrated Circuits (4th ed.). New York, USA: McGraw-Hill. CR - Karl, E., Wang, Y., Ng, Y. G., Guo, Z., Hamzaogly, F., Meterelliyoz, M., . . . Bohr, M. (2013). A 4.6 GHZ 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated, read and write assist circuitry. IEEE Journal of Solid-State Circuits, 48, 150-158. CR - Lundager, K., Zeinali, B., Tohidi, M., Madsen, J. K., & Moradi, F. (2016). Low power design for future wearable and implantable devices. Journal of Low Power Elektronics and Applications, 6(4), 1-20. CR - Pal, A. (2015). Low-Power VLSI Circuits and Systems (NA ed.). New Delhi, India: Springer. CR - Plummer, J. D., Deal, M. D., & Griffin, P. B. (2009). Silicon VLSI Technology: Fundamentals, Practise and Modeling (NA ed.). New Delhi, India: Pearson Education. CR - Rani, L. V., & Latha, M. M. (2016). Pass transistor-based pull-up/pull-down insertion technique for leakage power optimization in CMOS VLSI circuits. Circuts, System, Signal Processing, 35(11), 4139-4152. CR - Salman, E., & Friedman, E. G. (2012). High Performance Integrated Circuits Design (1st ed.). New York, USA: McGraw-Hill. CR - Sedra, A., & Smith, K. C. (2015). Microelectronic Circuits (8th ed.). New York, USA: Oxford University Press. Taur, Y., & Ning, T. H. (2013). Fundamentals of Modern VLSI Devices (2nd ed.). Cambridge, UK: Cambridge University Press. CR - Uddin, M. J., Nordin, A. N., Reaz, M. B., & Bhuiyan, M. A. (2013). A CMOS power splitter for 2.45 GHz ISM band RFID rider in 0.18 um CMOS technology. Tehnicki Vjesnik, 20(1), 125-129. CR - Weste, N. H., & Harris, D. M. (2011). CMOS VLSI Design: A Circuits and System Perspective (4th ed.). Boston, USA: Pearson Education. CR - Zant, P. V. (2014). Microchip Fabrication: A Practical Guide to Semiconductor Processing (6th ed.). New York, USA: McGraw-Hill. CR - Zeinali, B., Madsen, J. K., Raghavan, P., & Moradi, F. (2015). Sub-threshold SRAM design in 14 nm FinFET technology with impoved access time and leakage power. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, (pp. 74-79). Montpellier. CR - Zhang, H., Huang, M., Zhang, Y., Li, X., & Yoshihara, T. (2013). A nano-power switched-capacitor voltage reference using body effect in MOSFETs for application in subthreshold LSI. Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), (pp. 101-125). Hong Kong. UR - https://doi.org/10.28978/nesciences.358859 L1 - https://dergipark.org.tr/en/download/article-file/372350 ER -