VLSI Implementation of High Speed CMOS A/D Converters for Wireless Systems

Ali Tangel

Department of Electronics&Communication Eng.
University of Kocaeli, Veziroglu Kampusu 41040 Izmit, Turkey
atangel@kou.edu.tr

Abstract

This paper introduces and compares the high-speed CMOS ADC architectures from VLSI design point of view. The high speed ADCs are categorized into two groups as fully parallel and partially parallel structures. The principle of their operation, advantages and disadvantages are summarized. The study is concluded by a guide table for ADC designers. It is believed that this paper will be helpful especially for Mixed-Signal-VLSI ASIC designers when choosing the type of architecture they should implement in their designs according to the customer needs. The future trends in VLSI technology regarding high speed ADCs are also addressed.

Keywords: CMOS ADC, full-flash, semi-flash, pipeline, folding, interpolating, comparator