A CMOS Auto-Zero Comparator for High Speed&High Resolution Data Converters

Ali Tangel
and
Oktay Aytar

1,2 Dept. of Electronics & Communication Engineering
Kocaeli University, 41040 , Izmit, TURKEY
E-mail: {atangel,oktay}@kou.edu.tr

Abstract

In this paper, we present a novel low-power “Darlington-CMOS” inverter based auto zero comparator circuit to be used especially in flash ADC designs. The proposed CMOS inverter structure has more gain in transition region, resulting in a less number of analog switches in complete comparator comparing with traditional cascaded-stages auto-zero comparator. Simulation results include 0.335 mwatt of average power consumption, 100ns of worst case time delay for 2MHz analog input test signal under 100Ms/s sampling rate, and 0.026 mm2 of layout area in 0.5 mm CMOS nwell process. It is shown that the proposed auto zero comparator circuit can easily be used for over 6-bit flash type A/D converter designs as well as for other data converter implementations.

Keywords: flash ADC, auto-zero comparator, Darlington-CMOS inverter