Design Consideration for Active–Only Memcapacitor Emulator Circuits

—In this paper, a simple memcapacitor emulator circuit using only active elements is presented. Instead of using any bulky passive components, the proposed circuit makes use of the intrinsic capacitors of MOSFETs. As a result, the circuit took up significantly less area on the IC environment. In addition, a modification technique is proposed to extend the operating frequency range of the emulator, which might broaden the circuit's application possibilities. Considering the basic non-idealities of the circuit, a more realistic formulation of the memcapacitance value is derived. Detailed simulations utilizing the 0.18 µm CMOS Cadence design tool are used to validate all theoretical aspects as well as the circuit's appropriate functionality.

As the memristive elements are characterized by the wellknown pinched, or zero-crossing hysteresis twist in currentvoltage space, the fingerprint of the memcapacitor is the pinched loop in the voltage-charge space [11].In some implementation, memcapacitor behavior can be obtained using mutator which converts memristor behavior to memcapacitor [12][13].These circuits employ perfect memristor to implement the memcapacitor, which may be problematic in case the limitations of the involved memristor are not well understood or its optimized design is not available.The synthesis of memcapacitor using conventional building blocks, i.e. integrators, summing amplifiers, on the other hand, is a more prudent approach as the optimized basic building blocks are easily accessible [14][15][16][17].
At this point, it should be noted a well-known disadvantage of all these mem-element emulators for IC integration point of view, which stems from the implementation of the involved passive elements, suffer from large chip area [18][19][20].Activeonly circuit design is a very useful technique to address this drawback.In these circuits, passive components are realized using the intrinsic resistors and capacitors of the involved active components [21].While this approach substantially reduce the chip area occupied by the circuits, the circuit parameters can be adjusted electronically.
In this study an area efficient implementation of an integrator-based memcapacitor emulator (MC) is introduced.In order to have an area efficient solution, a design containing only active components is proposed.The benefits of the circuit are revealed by comparing it with similar circuits presented in the literature.Thanks to the evaluations of the main nonidealities of the proposed circuit, theoretical considerations which may help to assess the limitations of the proposed circuit are presented.Simulation results of the circuit using UMC 0.18 µm CMOS process are presented to illustrate the circuit performance.
In this paper, first the proposed realization of the memcapacitor emulator is presented.Then, the active element nonidealities are modeled and theoretical expressions are derived, which may be useful to assess the circuit important limitations.The operating frequency range of the proposed emulator is considered to be limited, which is partially mitigated by applying a modification technique.Simulation results justifying the proper operation of both the initial and the modified circuits are presented.Finally, a section with extensive comparisons of the suggested circuits to their counterparts is provided.

II. PROPOSED MEMCAPACITOR EMULATOR AND ITS PRELIMINARY DESIGN CONSIDERATIONS
The proposed memcapacitor, consisting of two active integrators built around a second generation current conveyor (CCII), a current controlled current conveyor (CCCII) and two voltage buffers is given in Fig. 1.Note that CCCII is actually a M EMRISTOR was first postulated by L. O. Chua as the missing circuit component in 1971 [1], is shown to be modified CCII, in which the intrinsic x-terminal resistance is included in its defining equation.
This resistance is given by: where µ  ,   are respectively the electron mobility and gate capacitor, while W/L is the transistor dimensions.The fact that this resistance can be controlled via the biasing current   is very beneficial from IC integration point of view.From Fig. 1, capacitors, CP1 and CP2 shown within the dashed lines are intrinsic capacitors which appear at the input port of the voltage buffers.While designing the circuit, transistors' dimensions at the input section of the voltage buffer are chosen big enough that these intrinsic capacitors become large and dominate other parasitic capacitors in the circuit.Moreover, in case the voltage buffers are implemented such that properly, these capacitors mainly stem from the gate capacitance of MOS transistors, these capacitors can be considered linear [22].Given the formal defining equations of CCCII and CCII, respectively [23],

Vin
and considering the fact that the input voltage   is small enough to satisfy (  ≪   −   ), the equivalent memcapacitance value of the proposed MC can be obtained as follows: The required multiplication operation is realized by the current-voltage relationship of the NMOS transistor arranged to operate in the triode region: By using (3) and ( 4) in ( 5), the equation is obtained as follows: The Eq.6 is rearranged as follows: By considering the charge-voltage relation of the capacitor element () =  (), and rearranging the equation, the value of memcapacitor becomes as follows: From Eq. 9, the value of the memcapacitance consists of two terms, one being time-dependent and the other is constant.Both of the terms can be electronically adjusted by changing  2 and  3 parameters, which may be beneficial in practical applications of the memcapacitance.
Copyright © BAJECE ISSN: 2147-284X http://dergipark.gov.tr/bajece In Table I, aspect ratios of the MOS transistors used in active devices are given.The CCCII active element is depicted in Fig. 2a and realized by using conventional translinear topology.To implement the CCII, input transistor with a very low   value is selected in accordance with Eq. 1. Voltage buffer is also shown in Fig. 2b.

III. NON-IDEAL ANALYSIS OF THE MEMCAPACITOR EMULATOR
Non-ideal model of the proposed memcapacitor is shown in Fig. 3. Considering the well-known non-idealities of the active elements, memcapacitor defining equation is obtained as follows [24]: ]  (10) In this expression,  1 () and  1 () are respectively, the nonideal current and voltage gains of CCII,  1 () is the non-ideal gain of the buffer, while  1 is the z-terminal parasitic resistance.
Extensive simulation results of the circuit in Fig. 2a shows that frequency dependency of  1 () and  1 () can be neglected, while  1 () can be represented with the following simple expression: For practical applications, the output resistance of the CCII satisfy the following: (1/ 1 ≪ | 1 |), thus Eq.10 can be approximated as: Considering the non-idealities of integrator-2, the equations are obtained as follows: Assuming that (1/ 2 ≪ | 2 |) and  2 () and  2 () are constant, Eq.13 can be obtained as: Using ( 12) into ( 14) yields: If the current-voltage relation of the NMOS transistor operating in the linear region is written and the Eq.15 is substituted in this relation, the memcapacitance relation is obtained as follows: As it can be seen from Eq.19, in the non-ideal case, the parasitics  1 ,  1 and  3 appear in parallel with the memcapacitor.In case, the circuit driving this memcapacitor has a lower output impedance, these effects can be neglected.Furthermore, the frequency dependency of the current gain, () may worsen the memory behavior of the element.Therefore, the circuit operating frequency range should be kept much smaller than the pole in the model of Eq. ( 19). .

IV. SIMULATION RESULTS
The simulation results of the proposed circuit are produced by using UMC 0.18 µm technology parameters in Cadence design environment.The active elements, CCII, CCCII and voltage buffers are supplied with ± 1V.Since the input current on the parasitic capacitor cannot be sensed, the hysteresis loop is simulated depending on the input voltage (  ) and  1 (  / 1 ) which is the first integrator output.An external sinusoidal signal with an amplitude of 200 mV is applied to the circuit to obtain the emulator characteristic.As shown in Fig. 4, the circuit generates the pinched hysteresis characteristic which is the fingerprint of membehavior.The sample characteristics are given at three different frequencies, at 60 MHz, 70 MHz and 80 MHz.
However, the simulation results for different biasing currents are also obtained in Fig. 5. From these results, it is seen that the circuit is capable of generating the memristor behavior over a wide range of the biasing current The change in the circuit performance against environmental temperature variations is also studied.The circuit dynamics at three different temperatures are obtained at 60 MHz and the results are given in Fig. 6.From these results, it is clear that the circuit is able to generate the mem-behavior over a wide range of temperature.In addition, simulation results at different processing corners are obtained at 60 MHz and are given in Fig. 7. From these results, the circuit works properly against the process changes.In order to reveal the dependency of the memcapacitance to the variation of the input signal, we have obtained the simulation result in Fig. 8.The memcapacitance depends on the input signal frequency, which is resulted from the nonlinearity of the memcapacitor.
Since intrinsic capacity is used instead of discrete capacity in this study, the capacity value varies between 100-500 fF.The rate of change is in the same order as circuits using discrete capacity [14].The proposed memcapacitor has an operating frequency range proportional to   /  .As we use an intrinsic capacitor with a small range of values to implement Cp, the operating frequency range of the circuit varies within a narrow range.To remedy this issue, capacitance multiplier is proposed in the literature [25].In this section, we applied this technique to the proposed emulator, in order to expand its operation frequency range, towards lower frequency region.
A conceptual capacitance multiplier built around CCII-is given in Fig. 9. CCII-refers to the negative output current conveyor and the constitutive equation is given as: where KC is the current gain from the x to z terminal currents of the current conveyors and equals 1 for conventional current conveyors.The current gain mentioned in this study should be taken as greater than 1.In this case, the equivalent input capacitance can be calculated using the following equation: Therefore, for   > 1, the equivalent capacity will be greater than the   capacity.The Kc value can be set to the desired value by appropriately arranging the size ratios of the M10-M11 and M12-M13 MOS current mirrors transistors in the translinear current conveyor which is shown in Figure 10.
By applying this technique to the proposed circuit, we obtain the modified circuit in Fig. 11.Assuming that the input terminal voltages of the current conveyors are equal, the memcapacitance of the circuit in Fig. 11 is as follows: To verify the feasibility of the approach, simulation results are obtained for the 80 MHz and 100 mV input sinusoid of the modified circuit.The observed pinched hysteresis loops obtained for KC =10 and KC =1 are shown in Fig. 12.Some figures which can be useful to compare the proposed circuit compared with its existing counterparts are presented in Table II.All existing counterpart's studies are used passive components, so they are not area efficient design.To the best of the authors knowledge, there is not any other active-only memcapacitor emulator in the literature.It provides a big advantage in terms of the IC design environment, as it takes up less space as there are no discrete components.
Copyright © BAJECE ISSN: 2147-284X http://dergipark.gov.tr/bajeceAs can be seen from Table II, the proposed circuit can operate at much higher frequencies and lower power supply rates than existing circuits.The proposed memcapacitor can be adjusted electronically in this study, as in some studies in Table II.The floating solution offers more flexible usage possibilities, but the grounded solutions are used more in practice because they have a simpler structure.

VII. CONCLUSION
In this study, an integrator-based memcapacitor emulator is presented.The important parameters of the proposed circuit can be adjusted electronically to the desired value.Compared to previous studies presented in the literature, the proposed memcapacitor has a structure consisting of only active building blocks.Therefore, the chip area will be smaller compared to their counterparts.The viability of the circuit is verified via detailed simulation results.Furthermore, a detailed nonideality analysis which reveals the main limitation of the circuit are presented.Finally, a modification technique which can be applied to extend the operating frequency range of the circuit is presented.

Fig. 1 .
Fig.1.The general topology of proposed MC topology

TABLE I ASPECT
RATIOS (in µm) OF THE TRANSISTORS IN FIG.2