FPGA Schematic Implementations and Comparison of FIR Digital Filter Structures

In this study, we investigate the FPGA schematic implementations of finite impulse response (FIR) digital filters for three fundamental structures on Altera DE2-115 board without requiring any other software packages such as DSP Builder and Matlab Simulink. First of all, a low pass FIR digital filter is designed by using Matlab filter design and analysis tool (fdatool) program. Then, the designed filter is implemented and simulated on Matlab for a given input signal. After that, for three fundamental structures (namely direct-form, transposed direct-form, and symmetric direct-form) in literature, the designed filter is implemented schematically on Quartus-II software and then each project containing different structure implementation is compiled. Then, the digital filters implemented by each structure are simulated by University Program Vector Wave File (VWF) simulation program on Quartus-II software. Simulation results show that the obtained results are the same as the ones obtained on Matlab, which confirms that the schematic designs are successfully implemented. Moreover, the implemented digital filters are realized and successfully tested on Altera DE2-115 FPGA board. Finally, three fundamental FIR structures for various filter lengths from 11 to 51 are implemented to compare them in terms of total logic elements, total registers, and total memory.


I. INTRODUCTION
IGITAL filters, which are one of the most important elements in Electronics Engineering applications such as communication, control, and biomedical systems, are used to remove or enhance selected frequency range in a digital signal.Digital filters are classified as finite impulse response (FIR) and infinite impulse response (IIR) according to the duration of impulse response [1].FIR filters are very popular because they can be designed as always stable and having exact linear phase.
FIR Digital filters can be implemented on the embedded systems such as microcontroller [2], digital signal processor (DSP) [3], and field programmable gate array (FPGA) [4].An FPGA is an integrated circuit in which hardware structure can be changed after production according to the desired function.FPGA technology is used in a wide spectrum area from consumer electronics to aerospace and defense industries [5].FPGA implementation of FIR filters can be provided by a hardware description language (VHDL or Verilog) or schematic description.And, there are recently proposed studies in literature on the implementation of FIR filters on FPGA [6][7][8][9], but they require some licensed software package.
In this study, we investigate the FPGA schematic implementations of FIR digital filters for three fundamental structures on Altera DE2-115 FPGA board without requiring any other software packages such as DSP Builder and Matlab Simulink.In Section 2, we briefly introduce FIR filters with their fundamental structures and then the software and hardware tools used in this study.We then describe our proposed FPGA schematic implementations in Section 3. The simulation and realization results for the proposed implementations are given in Section 4. Finally, conclusion part is presented in the last section.

II. MATERIALS AND METHODS
In this section, we first briefly describe the theoretical backgrounds of FIR filters and their fundamental structures.And then, the software tools and FPGA board used in this study are introduced.

A. FIR Filters
A causal N-length (or order with N-1) FIR digital filter can be characterized by the transfer function, H(z), which is the ztransform of the impulse response of the digital filter where Y(z) and X(z) are z-transforms of the input and output signals of the digital filter, respectively.And, h(n) and b coefficients represent the impulse response and filter coefficients of the digital filter, respectively.For an FIR filter, the impulse response values and the filter coefficients are always the same whereas they are different for an IIR filter.
An FIR filter can also be characterized by the difference equation which gives the relationship between the input and output signals of the digital filter in discrete time domain where x(n) and y(n) represent the input and output signals of the digital filter, respectively.

FPGA Schematic Implementations and Comparison of FIR Digital Filter Structures
O. Coşkun, and K. Avci D As compared to IIR filters, FIR filters have two main advantages which are about the stability and linear phase characteristics.FIR filters are always stable, because the poles of the transfer function are always on the origin of the z-plane which mean that they are inside the unit circle.And, FIR filters can be easily designed as having exact linear phase by providing that h(n) is symmetric or antisymmetric.
In literature, four general methods, namely optimization, windowing, frequency sampling, and numerical methods are used to design FIR filters to satisfy a prescribed characteristic [1].By using a software tool such as Matlab ©, FIR filters can be easily designed, i.e. the filter coefficients can be found.

B. Fundamental FIR Filter Structures
FIR digital filters can be implemented by three fundamental structures known as direct-form, transposed direct-form, and symmetric direct-form.Besides these, they can be implemented by some other structures such as cascade, parallel, lattice, etc. [1].In all digital filter implementation types, three circuit elements are used.These are the multiplier, adder, and delay.
The circuit for direct-form FIR structure for N length is shown in Fig. 1.It is called direct-form because it directly realizes the convolution process of an FIR filter.It is seen from the figure that total number of the delay elements is equal to the filter order (N-1), therefore this structure is a canonical type structure [1].In this structure, the input signal is first delayed by z -1 and then multiplied by b coefficients.
The circuit for transposed direct-form FIR structure for N length is shown in Fig. 2. It is called transposed direct-form because as opposed to the direct-form the input signal is first multiplied by b coefficients and then delayed by z -1 .This structure is also a canonical type structure.
The circuit for symmetric direct-form FIR structure for N length is shown in Fig. 3.The number of the multipliers in this structure is half of the ones in other two fundamental structures.This structure can be used only if the filter coefficients are symmetric.

D. Quartus II Software
The Quartus-II software produced by Altera is a programmable logic device design software, and it enables analysis and synthesis of HDL designs [11].In this study, Quartus-II is used to implement the digital filters schematically, to compile and simulate the digital filters, and to upload the necessary files to the FPGA board.We use Quartus-II 13.1 64 bit web edition as shown in Fig. 4.  In this section, we present the proposed schematic implementations for three fundamental FIR structures.
As can be seen from the circuits given by Fig. 1, Fig. 2, and Fig. 3, a digital FIR filter circuit consists of only three digital circuit elements which are multiplier, adder, and delay.Therefore, altemmult (Fig. 6a), parallel_add (Fig. 6b), and 74273b D-flip-flop (Fig. 6c) block schemes are chosen from the Quartus II software library for implementing the elements of multiplier, adder, and delay, respectively.In this section, we present the simulations performed on Matlab and Quartus II environments and then compare with realization performed on the FPGA board.

A. Matlab Simulation Results
To be able to simulate a digital filter and then implement it on an FPGA, we first need to design that filter by using a software program.For this purpose, a lowpass FIR filter based on Kaiser window [13] for beta = 1 is designed by using Matlab fdatool for the filter length N=5 (or filter order = 4), sampling frequency fs=1000 Hz, and cut off frequency fc=100 Hz as seen in Fig. 10.
The five non-integer filter coefficients found from the fdatool are given in Fig. 11a.These coefficients are then rounded to be integer as in Fig. 11b.
The test signal which will be used as an input to the designed filter for the simulation and realization example is shown in Fig. 12a.When this input signal is applied to the designed filter which is also defined by its impulse response in Fig. 12b, the output signal is obtained as shown in Fig. 12c.It is seen that the steady state filtered value is 1000 in decimal which will be used to evaluate the proposed FPGA implementations of the digital filter.

B. Quartus-II Simulation Results
First of all, a Quartus-II project including the schematic implemented direct-form FIR structure given Fig. 7 is prepared and then compiled.After that, it is simulated by using University Program Waveform in Quartus II.The obtained simulation result is shown in Fig. 13.
It is seen from the figure that the output signal has transient values of 0, 151, 374, 626, and 849 and also has a steady state value of 1000.These results are exactly the same as the ones in Matlab simulation given by Fig. 12c.Two more Quartus-II projects for the schematic implemented transposed direct and symmetric direct forms of FIR structures given in Fig. 8 and Fig. 9 are also prepared and then compiled and simulated as in case for the direct-form.It is observed that the simulation results for the transposed direct and symmetric direct forms are also the same as the one given in Fig. 13.These simulation results demonstrate that our proposed FPGA schematic implementations for FIR structures given by Fig. 7, Fig. 8, and Fig. 9 are proper implementations.

C. Realization on DE-2 115 FPGA Board
To test the schematically implemented FIR structure on FPGA board, first the pins for the input x and output y signals are assigned as shown in Fig. 14 by using Assignment Editor in Quartus II.This process results in the switches from SW0 to SW8 on the board to be the input and clock signals, and also in the leds from LEDR0 to LEDR10 to be the output signal.
After making pin assignments, the project for direct-form is compiled again for realization test.Then, by using the programmer interface in Quartus II, the related .sofextended file is loaded to the FPGA board as shown in    16 shows that when the switches for the input signal are arranged to be '00000001', the obtained filtered value from LEDs is read as 01111101000 in binary which is equal to 1000 in decimal.This means that the realization of schematic implemented direct-form FIR structure is successfully working, since the realization result is the same as both Matlab © and Quartus-II simulation results.The same successful results are obtained for other two FIR structures as well.

Fig. 10 .
Fig.10.Low pass FIR filter design using Kaiser window [10,11] for window length N=5 (or filter order = 4) and cut off frequency fc=100 Hz Fig 15.a.If the loading progress is successful as in Fig 15.b, the realization test can be performed.

Fig. 13 .
Fig.13.Simulation result for the direct-form FIR structure for the filter with N=5 on Quartus-II

Fig.
Fig.16shows that when the switches for the input signal are arranged to be '00000001', the obtained filtered value from LEDs is read as 01111101000 in binary which is equal to 1000 in decimal.This means that the realization of schematic implemented direct-form FIR structure is successfully working, since the realization result is the same as both Matlab © and Quartus-II simulation results.The same successful results are obtained for other two FIR structures as well.

Fig. 16 .
Fig.16.Realization result for the direct-form FIR structure for the designed filter with N=5 on Altera DE-2 115 FPGA board