DIGITALLY PROGRAMMABLE MULTI-SCROLL CHAOS GENERATOR ON FPGA

Multi-scroll chaotic attractors exhibit higher unpredictability than double-scroll attractors. However, the more number of scrolls cost the more usage of sources. To overcome this problem, the attractor design should be simplified. This paper presents a systematic approach that enables to realize digital piece wise linear (PWL) function in nonlinear dynamical system and to obtain whole behaviors in only one model. The proposed design requires only number of scroll as input and can realize chaotic PWL signal with a fewer number of FPGA resources. In the implementation stage of the study, the discrete mathematical equations of the chaotic attractor is modelled in Xilinx System Generator (XSG) platform and realized by using Xilinx Kintex-7 KC705 Evaluation Board.

In this study, a systematic approach that enables to realize digital piece wise linear (PWL) function in the Chua's circuit model and to obtain whole behaviors in only one model. The proposed multi-scroll chaotic attractors design requires only number of scroll as input and can realize chaotic PWL signal with a fewer number of FPGA resources. In the implementation stage of the study, the discrete mathematical equations of the chaotic system is modelled in Xilinx System Generator (XSG) platform and realized by using Xilinx Kintex-7 KC705 Evaluation Board.
Herewith this introduction, in Section 2, the Chua's circuit is described and MATLAB-Simulink model is executed and chaotic behavior of the multi-scroll chaotic attractors are obtained. Section 3 includes the discretization method, Xilinx System Generator designs and realization of the system. At the end, Section 4 concludes the paper.

The Chua's Circuit
The Chua's circuit is the simplest electronic chaotic circuit that has only one nonlinear component called nonlinear resistor. The circuit diagram is shown in Fig. 1 and can be described by the following set of dynamical equations as proposed in [5,6]; where IL, V2 , V1 , mi and bi stand for current of inductor, the voltages across C2 and C1 , the slope of the i-th segment and the breakpoints of the nonlinear resistor, respectively [17]. The nonlinear PWL function is represented as f(.) and has two components fe(.) and fo(.) that are the function for the case of even and odd number of scrolls respectively. Therefore, the system can change its behavior regarding to number of scrolls. Furthermore, the system parameters are given as m0 = -3.2 ms, m1 = m3 = m5 = m7 = m9 = -0.2 ms, m2 = m4 = m6 = m8 = -2.2 ms, C1 = 10 nF, C2 = 100 nF and L = 18.68 mH. The multi-scroll chaotic attractors are obtained according to the number of scrolls, the breakpoint voltages and resistor values. Table 1 shows the value of resistor and the breakpoint voltages in contrast to number of scrolls.
The differential equations of the system can be simulated on MATLAB Simulink platform to observe system behavior in contrast to number of scrolls [22,23]. The MATLAB Simulink model has three sub blocks that are tank resonator, PWL and control blocks. The tank resonator block consists of dynamical Chua's circuit equations except for PWL function f(.). The control unit decides which output of PWL block to transmit to the tank resonator according to the scroll value applied to the control unit input. The system behaviors for 9 and 10 scrolls are obtained regarding to system parameters given in Fig. 3. Before execution of Simulink model given in Fig. 2, the values of resistor and scroll must be typed in MATLAB command window as given in Table 1.

Discretization of differential equations
In digital applications, researchers use discrete time modelling in order to embed the system to embedded systems such as microprocessors, FPGA, ARM and so on. There are three types of discretization methods that are Taylor series expansion, Runge-Kutta and Euler integration methods [24]. In this study, Forward Euler integration method is used to discretize the dynamical Chua's circuit equations.
The expression of FE method is given in Eq. 3 and discretized model is expressed in Eq. 4 and 5 with the time step h;

Design and realization
In the design stage, discretized equations of chaotic Chua's circuit is modelled on XSG platform by using standard XSG arithmetic blocks. XSG blocks use fixed-point number format. Therefore, 32bit signed fractional numbers are used in arithmetic operations such as addition and multiplication process of the design. Qm.n is used for representing fixed-point number format where m indicates the number of bits that are arranged for integer part of number while n for fractional part. Therefore, the format is arranged as Q16. 16 to get resolution as 2 -n = 2 -16 = 1.5259 e-5. Fig. 4, 5, 6 and 7 illustrate the XSG design of the discretized tank resonator, control unit, PWL (even) and subsystem of the PWL (even), respectively. The tank resonator XSG design requires only one input that is one of the PWL function (odd or even). The whole design is constructed with adder, multiplier, constant, multiplexer, slice, gateway in/out, input/output, register and absolute value blocks. The initial conditions of state variables are given as (IL, V2, V1) = (0, 0, 0.01).
The control unit determines whether the value of scroll is even or odd using multiplexer. If the value of the scroll is even, output value of PWL (even) block is transmitted to tank resonator input or vice versa in each iteration. In the Fig. 8, chaotic attractor behaviours for 9 and 10 scrolls are obtained regarding to system parameters by executing XSG simulation. In the implementation stage of study, Xilinx Kintex-7 Evaluation Board is connected to the host computer via JTAG cable to obtain hardware based cosimulation process.  Hardware Co-simulation process is executed on selected FPGA board to determine whether the design can be realized or not. Whole parts of design is merged to one design file and it is shown in Fig.  9. For an example of study, the multi-scroll attractor design is co-simulated and realized for 5-scroll and the design is given in Fig. 10. As it can be seen that JTAG Hardware Co-simulation block is also added to design. As a result of this study, Fig. 11 shows realization of the chaotic attractor for 5-scroll. The multi-scroll chaotic attractor is realized in XSG JTAG Hardware Co -simulation platform and Table 2 shows the resource utilization of the attractor for 5 -scroll.

Conclusions
In this study, the chaotic Chua's circuit is simulated in MATLAB, discretized using Forward Euler discretization method and modelled on XSG platform. The advantages of our study are that the design is realized on FPGA with fewer number of resource, requires only the number of scroll as input and is fully programmable. Therefore, the design can be easily adapted to secure communication and synchronization circuits.