Novel and Low-Cost Techniques for Extending the Etch Capabilities of an Inductively Coupled Plasma Etch Tool That Has Clamp Fingers for Clamping 4-Inch Diameter Wafers

Abstract

Widening the processing capabilities of an inductively coupled plasma (ICP) etch tool by “preventing wafer breakage” during processing of wafers, or by gaining the capability to do “through-wafer silicon etch” are important challenges that may need to be resolved with very limited resources. Resolving the undesired wafer breakage issues caused during processing of wafers is important to reduce the manufacturing costs, and increase production yield. Furthermore, considering the high prices of the state-of-the-art wafer processing tools, it is also important to prevent wafer breakage by using low-cost approaches especially if the resources for purchasing state-of-the-art processing equipment are not available. Two novel methods (method #1, and method #2) are developed to prevent wafer breakage and allow through-wafer silicon etching. With method #1, an aluminium alloy ring (AAR) and an o-ring are employed to obtain uniform load distribution (instead of point loads) on the required outer region on the surface of a wafer, and to minimize or completely remove the bending moment that may be formed on the possible cross-sections of the entire wafer, during clamping of the wafer. With method #2, through-wafer silicon etching is made possible by simultaneous application of method #1 and addition of a helium cooling gas (HCG) leakage blocking dicing tape at the back side of the wafer that is under processing for through-wafer etching. By using the explained methods, wafer breakage during ICP etch processing is eliminated, and through-wafer silicon etching is made possible. From the other side, the effective wafer area that can be used for processing is reduced by 48%. Novel and capability enabling 2 different techniques that are extremely low-cost compared to purchasing a state-of-the-art ICP etch tool are presented to extend the processing capabilities of an ICP etch tool for deep silicon etching (method #1), and through-wafer silicon etching (method #2).

Keywords

• Low-cost
• Inductively coupled plasma (ICP)
• Wafer breakage
• Wafer breakage prevention
• Wafer breakage-free
• Through-wafer silicon etch

References

1. Bonfim MJC, Swart JW, Velasco CEM, Okura JH, Verdonck PB. 1993. A low frequency remote plasma rapid thermal CVD system with face down electrostatic clamp wafer holder. In: Spring Meeting of the Materials Research Society, Symposium on Rapid Thermal and Integrated Processing II, April 12-15, San Francisco, CA, USA, 303: 407–412.
2. Brun XF, Melkote SN. 2009. Analysis of stresses and breakage of crystalline silicon wafers during handling and transport. Sol Energy Mater Sol Cells, 93 (8): 1238-1247.
3. Chen P-Y, Chen SL, Tsai MH, Jing MH, Lin T-C. 2007. Investigation of wafer strength in 12 inch bare wafer for prevent wafer breakage. In: Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits, December 20-22, Tainan, Taiwan, pp: 545-548.
4. Chen P-Y, Tsai MH, Yeh WK, Jing MH, Chang Y. 2010. Relationship between wafer fracture reduction and controlling during the edge manufacturing process. Microelectron Eng, 87 (10): 1809-1815.
5. Chowdhury S, Wu Y, Shen L, McCarthy L, Parikh P, Rhodes D, Hosoda T, Kotani Y, Imanishi K, Asai Y, Ogino T, Kiuchi K. 2020. 5000+Wafers of 650 V highly reliable GaN HEMTs on Si substrates: wafer breakage and backside contamination results. In: 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), August 24-26, Saratoga Springs, NY, USA, pp: 3.
6. Corial. 2024. Deep reactive ion etching (DRIE). URL: https://corial.plasmatherm.com/en/technologies/drie-deep-reactive-ion-etching (accessed date: July, 09, 2024).
7. Izyumov M. 2009. An electrostatic clamp with temperature stabilization of semiconductor wafers under plasma treatment. Instrum Exp Tech, 52: 886-887.
8. Liu T, Su Y, Ge P. 2022. Breakage ratio of silicon wafer during fixed diamond wire sawing. Micromachines, 13(11): 1-13.

9. McLaughlin JC, Willoughby AFW. 1987. Fracture of silicon wafers. J Cryst Growth, 85(1-2): 83-90.
10. Meyer T, Petit-Etienne C, Pargon E. 2022. Influence of the carrier wafer during GaN etching in Cl2 plasma. J Vac Sci Technol A, 40: 023202.
11. Nabavi R, Sarraf S, Soltanieh M. 2023. Optimization of hard anodizing process parameters on 6061-T6 aluminum alloy using response surface methodology. J Mater Eng Perform, 2023: 1-14. https://doi.org/10.1007/s11665-023-08717-4.
12. Noori Y, Skandalos I, Yan X, Zhelev N, Hou Y, Gardes F. 2024. Wafer bonding for processing small wafers in large wafer facilities. IEEE Trans Compon Pack Manuf Technol, 14 (2): 342-348.
13. Oxford Instruments. 2024. Inductively coupled plasma etching (ICP RIE). URL: https://plasma.oxinst.com/technology/icp-etching (accessed date: July, 09, 2024).
14. Plasma-Therm. 2024. Inductively coupled plasma (ICP) technology for etching high etch rates, process flexibility and reduced ion bombardment. URL: https://www.plasmatherm.com/process/etch/icp/ (accessed date: July, 09, 2024).
15. Saffar S, Gouttebroze S, Zhang ZL. 2015. Stress and fracture analyses of solar silicon wafers during suction process and handling. J Sol Energy Eng Trans-ASME, 137(3): 031010.
16. Sentech. 2024. Plasma etching. URL: https://www.sentech.com/products/plasma-process-technology/plasma-etching/ (accessed date: July, 09, 2024).
17. Silyb Wafer Services, Inc. 2023. What are the main causes of silicon wafer breakage? URL: https://www.silybwafers.com/what-are-the-main-causes-of-silicon-wafer-breakage (accessed date: July, 09, 2024).
18. SPTS. 2024. Plasma etch. URL: https://www.spts.com/categories/plasma-etch (accessed date: July, 09, 2024).
19. Wafer World Inc. 2021. Top causes of silicon wafer breakage. URL: https://www.waferworld.com/post/top-causes-of-silicon-wafer-breakage (accessed date: July, 09, 2024).
20. Yang Y-J, Kuo W-C, Fan K-C. 2006. Single-run single-mask inductively-coupled-plasma reactive-ion-etching process for fabricating suspended high-aspect-ratio microstructures. Jpn J Appl Phys, 45(1A): 305-310.
21. Zhou L, Qin F, Sun J, Chen P, Yu H, Wang Z, Tang L. 2015. Fracture strength of silicon wafer after different wafer treatment methods. In: 16th International Conference on Electronic Packaging Technology (ICEPT), August 11-14, Changsha, China, pp: 871-874.