A Majority Gate Based RAM Cell design with Least Feature Size in QCA

Year 2019, Volume: 32 Issue: 4, 1150 - 1165, 01.12.2019

Amanpreet Sandhu Sheifali Gupta

https://doi.org/10.35378/gujs.500724

Cited By: 4

Abstract

Designing and fabricating complementary metal-oxide
semiconductor (CMOS) based logic devices at nanoscale
faces serious issues like oxide thickness, thermal reliability, and energy
dissipation. Hence the industries are in search of new technologies which could
substitute the scaling down of CMOS circuits. Quantum-dot-cellular-automata
(QCA) is an imminent technology considered at nano-level with the
high speed of operation and lower power dissipation features. As the memory is
used in most of the electronic equipment for data storage purpose, designing a
RAM cell with a reduced number of QCA cells, and lower energy dissipation finds
wide applications in the electronics industry. This paper first proposes a
five input majority gate which may be utilized efficiently for designing single
layer QCA circuits. Then by using the invented gate, a coplanar RAM cell structure with Set and
Reset capability is devised. The structural
and energy dissipation analysis
of presented structures are estimated using QCADesigner
and QCAPro tools. The results prove that the disclosed RAM cell architecture
achieves 12.5% lower area, 18.26% lower
total energy dissipation, and 16.6% lower input to output delay than the best-reported design.

Keywords

Quantum-Dot Cellular-Automata (QCA), Majority Gate, RAM cell, QCADesigner, QCAPro

References

• Reference 1 Gurmohan Singh, Senior Engineer, CDAC, Mohali
• Reference 2 Saket Srivastava, Senior Lecturer, University of Lincoln
• Reference 3 Sudeep Sarkar, Professor of Computer Science and Engineering, University of South Florida, Tampa