FPGA TABANLI SYSTEMLERDE KULLANILAN TOPLAYICILARIN MALYYET VE BA?ARIM DE?ERLENDYRMESY

Year 2011, Volume: 6 Issue: 4, 73 - 84, 01.05.2011

İbrahim Şahin Süleyman Çakıcı Pakize Erdogmus

Abstract

Sayysal tasarymlaryn ba?arymyny büyük ölçüde etkileyen önemli bile?enlerden birisi de ikili toplayycylardyr. Literatürde önerilen birçok toplayycy türü bulunmaktadyr. Bu çaly?mada, ikisi IP Core Generator tarafyndan olu?turulmu? üçü ise tasarlanmy? toplam be? farkly toplayycynyn iki farkly FPGA yongasy üzerinde ba?arym ve maliyet de?erlendirmesi yapylmy?tyr. En iyi ba?arymy DSP48Es bloklary kullanylarak IP Core Generator tarafyndan olu?turulan toplayycylaryn sundu?u tespit edilmi?tir. Tasarlanan toplayycylar arasynda ise "carry select adder" her iki yonga üzerinde de di?erlerine oranla daha yüksek ba?arym göstermi?tir. Di?er taraftan, beklenilenin aksine, donanym gereksiniminin di?er iki tasarlanan toplayycy ile ayny miktarda oldu?u görülmü?tür. Bu çaly?madan elde edilen di?er bir önemli sonuç ise, toplayycylaryn gerçeklenmesinde büyük arama tablolarynyn (Look-Up Tables) kullanylmasynyn toplayycy maliyetinde beklenen ölçüde iyile?me sa?lamamasydyr.

Keywords

Ykili toplayycylar, Maliyet, Ba?arym, FPGA, VHDL,

PERFORMANCE AND COST EVALUATIONS OF ADDERS USED IN FPGA-BASED SYSTEMS

Abstract

One important component of the most digital designs is binary adders which greatly affects the total performance of the designs. In the literature several different types of adders were proposed. In this study, performance and cost evaluations of five selected adders, two of which were generated using IP Core Generator and three of which were designed adders, were done on two selected FPGA chips. The results show that, the adders generated using the IP Core Generator with DSP48Es block are the best in most cases. Among the three non-generated adders, the carry select adder showed slightly better performance on average on both chips than others. On the other hand, in contrary to the expectations, it costs about the same amount of hardware with the other two. Another outcome of this study is that using larger Look-up Tables did not improve the costs of the designed adders as much as expected.

Keywords

Binary adders, Cost, Performance, FPGA, VHDL,