saujs Sakarya University Journal of Science 2147-835X Sakarya University 10.16984/saufenbilder.877453 Electrical Engineering Elektrik Mühendisliği Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA https://orcid.org/0000-0001-9277-3796 Baran Dursun TÜRKİYE BİLİMSEL ve TEKNOLOJİK ARAŞTIRMA KURUMU 12 31 2021 25 6 1386 1393 02 09 2021 11 02 2021 Copyright © 1997, Sakarya University Journal of Science 1997 Sakarya University Journal of Science

Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.

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