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## A process-tolerant low-power adder architecture for image processing applications

#### Bharat GARG [1] , G K SHARMA [2]

The aggressive CMOS technology scaling in the sub-100-nm regime leads to highly challenging VLSI design due to the presence of unreliable components. The delay failures in arithmetic units are increasing rapidly due to the increased effect of process variation (PV) in scaled technology. This paper introduces a novel process-tolerant low-power adder (Prot-LA) architecture for error-tolerant applications. The proposed Prot-LA architecture segments the operands into two parts and computes addition of the upper parts in carry-propagate, whereas it computes the lower parts in a carry-free manner. In the Prot-LA, the number of bits in carry-propagate and carry-free additions can be reconfigured based on the amount of PV. An on-chip PV detector is embedded to determine the PV severity. Because of this reconfigurability, the proposed adder completes the carry propagation with minimum error even under severe process variation. The simulation results show that proposed Prot-LA provides 19.9 % reduced power consumption over the state-of-the-art approximate adder. The efficacy of the proposed adder is demonstrated in the real application by designing an image scaling processor (ISP). The simulation results show that the Prot-LA embedded ISP consumes 7.75 % reduced energy with 2.43 dB higher PSNR over the existing approximate adder embedded ISP.
Low power, approximate designs, process variation, error-resiliency, image scaler
Journal Section Articles Author: Bharat GARG Author: G K SHARMA Publication Date : June 1, 2019
 Bibtex @ { tbtkelektrik577538, journal = {Turkish Journal of Electrical Engineering and Computer Science}, issn = {1300-0632}, eissn = {1303-6203}, address = {}, publisher = {TUBITAK}, year = {2019}, volume = {27}, pages = {1839 - 1854}, doi = {}, title = {A process-tolerant low-power adder architecture for image processing applications}, key = {cite}, author = {GARG, Bharat and SHARMA, G K} } APA GARG, B , SHARMA, G . (2019). A process-tolerant low-power adder architecture for image processing applications. Turkish Journal of Electrical Engineering and Computer Science , 27 (3) , 1839-1854 . Retrieved from https://dergipark.org.tr/en/pub/tbtkelektrik/issue/45742/577538 MLA GARG, B , SHARMA, G . "A process-tolerant low-power adder architecture for image processing applications". Turkish Journal of Electrical Engineering and Computer Science 27 (2019 ): 1839-1854 Chicago GARG, B , SHARMA, G . "A process-tolerant low-power adder architecture for image processing applications". Turkish Journal of Electrical Engineering and Computer Science 27 (2019 ): 1839-1854 RIS TY - JOUR T1 - A process-tolerant low-power adder architecture for image processing applications AU - Bharat GARG , G K SHARMA Y1 - 2019 PY - 2019 N1 - DO - T2 - Turkish Journal of Electrical Engineering and Computer Science JF - Journal JO - JOR SP - 1839 EP - 1854 VL - 27 IS - 3 SN - 1300-0632-1303-6203 M3 - UR - Y2 - 2020 ER - EndNote %0 Turkish Journal of Electrical Engineering and Computer Science A process-tolerant low-power adder architecture for image processing applications %A Bharat GARG , G K SHARMA %T A process-tolerant low-power adder architecture for image processing applications %D 2019 %J Turkish Journal of Electrical Engineering and Computer Science %P 1300-0632-1303-6203 %V 27 %N 3 %R %U ISNAD GARG, Bharat , SHARMA, G K . "A process-tolerant low-power adder architecture for image processing applications". Turkish Journal of Electrical Engineering and Computer Science 27 / 3 (June 2019): 1839-1854 . AMA GARG B , SHARMA G . A process-tolerant low-power adder architecture for image processing applications. Turkish Journal of Electrical Engineering and Computer Science. 2019; 27(3): 1839-1854. Vancouver GARG B , SHARMA G . A process-tolerant low-power adder architecture for image processing applications. Turkish Journal of Electrical Engineering and Computer Science. 2019; 27(3): 1854-1839.