Araştırma Makalesi
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Yıl 2019, Cilt: 32 Sayı: 2, 572 - 580, 01.06.2019

Öz

Kaynakça

  • [1] Garginie. P, “Roadmap Past, Present and Future,” https://linxconferences.com/wp-content/uploads/2016/04/02-01-Gargini- ITRS-2.0-2.pdf/, 2015, [Online; accessed May-2015].
  • [2] Girard. P, “Survey of low-power testing of VLSI circuits,” IEEE Des. test, 19(3), 82–92, (2002).
  • [3] Girard. P, Nicolici. N and Wen. X, Power-Aware Testing and Test Strategies for Low Power Devices, 1st ed. Springer Publishing Company, Incorporated, 2009.
  • [4] Bota. S. A., Rossello J.L, De Benito. C, Keshavarzi. A and Segura. J, “Impact of thermal gradients on clock skew and testing,” IEEE Design & Test of Computers, 23(5), 414–424, (2006).
  • [5] Cho. M and Pan. D. Z, “Peakaso: Peak-temperature aware scan-vector optimization”, in Proceedings of IEEE VLSI Test Symposium, (2006).
  • [6] Dutta. A, Kundu. S, and Chattopadhyay. S, “Test vector reordering to reduce peak temperature during testing”, in Annual IEEE India Conference (INDICON), 1–6, (2013).
  • [7] Yoneda. T, Nakao. M, Inoue. M, Sato. Y, and Fujiwara. H, “Temperaturevariation-aware test pattern optimization,” in 16th IEEE European Test Symposium (ETS), 214–214, (2011).
  • [8] Dutta. A, Kundu. S, and Chattopadhyay. S, “Thermal aware don’t care filling to reduce peak temperature and thermal variance during testing,” in 22nd Asian Test Symposium, 25–30, (2013).
  • [9] Chandra. A and Chakrabarty. K, “Test data compression and test resource partitioning for system-on-a-chip using frequency-directed runlength (FDR) codes,” IEEE Transactions on Computers, 52(8), 1076-1088, (2003).
  • [10] Yuan. H, Guo. K, Sun. X, and Ju. Z, “A power efficient test data compression method for soc using alternating statistical run-length coding,” Journal of Electronic Testing, 32(1), 59–68, (2016).
  • [11] Sankaralingam R, Oruganti R.R, and Touba. N.A, “Static compaction techniques to control scan vector power dissipation,” in Proceedings of IEEE VLSI Test Symposium, 35–40, (2000).
  • [12] Hamzaoglu. I and Patel. J, H, “Test set compaction algorithms for combinational circuits,” in Proceedings of ACM international conference on Computer-aided design. ACM, 283–289, (1998).
  • [13] Stan. M. R, Skadron. K, Barcella. M, Huang. W, Sankaranarayanan. K, and Velusamy. S, “Hotspot: A dynamic compact thermal model at the processor-architecture level,” Microelectronics Journal, 34(12), 1153–1165, (2003).
  • [14] Brglez. F, Bryan. D, and Kozminski. K, “Combinational profiles of sequential benchmark circuits,” in IEEE International Symposium on Circuits and Systems, 1929–1934, (1989).
  • [15] Pathak. S, Grover. A, Pohit. M, and Bansal. N, “Locco-based scan chain stitching for low-power dft,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(11), 3227–3236, (2017).
  • [16] Synopsys Inc., Design Compiler User Guide, Version B-2008.09 (September 2008).
  • [17] Synopsys Inc., Power Compiler User Guide, Version D-2010.03-SP2 (June, 445 2010).

Temperature-Aware X-filling for Very Large Scale Integrated Circuits

Yıl 2019, Cilt: 32 Sayı: 2, 572 - 580, 01.06.2019

Öz

The
excess switching activity during testing increases the power dissipation beyond
the normal operation of the circuit. The non-linear power distribution creates
localized heating called hotspot which results in the structural damage and
increased cooling package cost. The temperature of a particular block depends
on heat generation and dissipation of the circuit blocks. The uniformity in
power distribution among the circuit blocks is the key requirement for
temperature reduction. The unspecified bits present in the test patterns are utilized
to reduce the switching activity during testing. In this paper, we present an
event-driven based power analysis and temperature aware X-filling to reduce the
total power dissipation among the circuit blocks in such a way to reduce peak
temperature. To reduce the peak temperature, the power dissipation of each
block is monitored with the help of fillings the X-bits. The experiments are
carried out with the ISCAS’89 benchmark circuit and show a significant
reduction in peak temperature and ensure uniform power distribution during
testing.

Kaynakça

  • [1] Garginie. P, “Roadmap Past, Present and Future,” https://linxconferences.com/wp-content/uploads/2016/04/02-01-Gargini- ITRS-2.0-2.pdf/, 2015, [Online; accessed May-2015].
  • [2] Girard. P, “Survey of low-power testing of VLSI circuits,” IEEE Des. test, 19(3), 82–92, (2002).
  • [3] Girard. P, Nicolici. N and Wen. X, Power-Aware Testing and Test Strategies for Low Power Devices, 1st ed. Springer Publishing Company, Incorporated, 2009.
  • [4] Bota. S. A., Rossello J.L, De Benito. C, Keshavarzi. A and Segura. J, “Impact of thermal gradients on clock skew and testing,” IEEE Design & Test of Computers, 23(5), 414–424, (2006).
  • [5] Cho. M and Pan. D. Z, “Peakaso: Peak-temperature aware scan-vector optimization”, in Proceedings of IEEE VLSI Test Symposium, (2006).
  • [6] Dutta. A, Kundu. S, and Chattopadhyay. S, “Test vector reordering to reduce peak temperature during testing”, in Annual IEEE India Conference (INDICON), 1–6, (2013).
  • [7] Yoneda. T, Nakao. M, Inoue. M, Sato. Y, and Fujiwara. H, “Temperaturevariation-aware test pattern optimization,” in 16th IEEE European Test Symposium (ETS), 214–214, (2011).
  • [8] Dutta. A, Kundu. S, and Chattopadhyay. S, “Thermal aware don’t care filling to reduce peak temperature and thermal variance during testing,” in 22nd Asian Test Symposium, 25–30, (2013).
  • [9] Chandra. A and Chakrabarty. K, “Test data compression and test resource partitioning for system-on-a-chip using frequency-directed runlength (FDR) codes,” IEEE Transactions on Computers, 52(8), 1076-1088, (2003).
  • [10] Yuan. H, Guo. K, Sun. X, and Ju. Z, “A power efficient test data compression method for soc using alternating statistical run-length coding,” Journal of Electronic Testing, 32(1), 59–68, (2016).
  • [11] Sankaralingam R, Oruganti R.R, and Touba. N.A, “Static compaction techniques to control scan vector power dissipation,” in Proceedings of IEEE VLSI Test Symposium, 35–40, (2000).
  • [12] Hamzaoglu. I and Patel. J, H, “Test set compaction algorithms for combinational circuits,” in Proceedings of ACM international conference on Computer-aided design. ACM, 283–289, (1998).
  • [13] Stan. M. R, Skadron. K, Barcella. M, Huang. W, Sankaranarayanan. K, and Velusamy. S, “Hotspot: A dynamic compact thermal model at the processor-architecture level,” Microelectronics Journal, 34(12), 1153–1165, (2003).
  • [14] Brglez. F, Bryan. D, and Kozminski. K, “Combinational profiles of sequential benchmark circuits,” in IEEE International Symposium on Circuits and Systems, 1929–1934, (1989).
  • [15] Pathak. S, Grover. A, Pohit. M, and Bansal. N, “Locco-based scan chain stitching for low-power dft,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(11), 3227–3236, (2017).
  • [16] Synopsys Inc., Design Compiler User Guide, Version B-2008.09 (September 2008).
  • [17] Synopsys Inc., Power Compiler User Guide, Version D-2010.03-SP2 (June, 445 2010).
Toplam 17 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Mühendislik
Bölüm Electrical & Electronics Engineering
Yazarlar

Sivanantham Sathasıvam 0000-0002-1010-5178

Thilagavathi Karunamurthy

Yayımlanma Tarihi 1 Haziran 2019
Yayımlandığı Sayı Yıl 2019 Cilt: 32 Sayı: 2

Kaynak Göster

APA Sathasıvam, S., & Karunamurthy, T. (2019). Temperature-Aware X-filling for Very Large Scale Integrated Circuits. Gazi University Journal of Science, 32(2), 572-580.
AMA Sathasıvam S, Karunamurthy T. Temperature-Aware X-filling for Very Large Scale Integrated Circuits. Gazi University Journal of Science. Haziran 2019;32(2):572-580.
Chicago Sathasıvam, Sivanantham, ve Thilagavathi Karunamurthy. “Temperature-Aware X-Filling for Very Large Scale Integrated Circuits”. Gazi University Journal of Science 32, sy. 2 (Haziran 2019): 572-80.
EndNote Sathasıvam S, Karunamurthy T (01 Haziran 2019) Temperature-Aware X-filling for Very Large Scale Integrated Circuits. Gazi University Journal of Science 32 2 572–580.
IEEE S. Sathasıvam ve T. Karunamurthy, “Temperature-Aware X-filling for Very Large Scale Integrated Circuits”, Gazi University Journal of Science, c. 32, sy. 2, ss. 572–580, 2019.
ISNAD Sathasıvam, Sivanantham - Karunamurthy, Thilagavathi. “Temperature-Aware X-Filling for Very Large Scale Integrated Circuits”. Gazi University Journal of Science 32/2 (Haziran 2019), 572-580.
JAMA Sathasıvam S, Karunamurthy T. Temperature-Aware X-filling for Very Large Scale Integrated Circuits. Gazi University Journal of Science. 2019;32:572–580.
MLA Sathasıvam, Sivanantham ve Thilagavathi Karunamurthy. “Temperature-Aware X-Filling for Very Large Scale Integrated Circuits”. Gazi University Journal of Science, c. 32, sy. 2, 2019, ss. 572-80.
Vancouver Sathasıvam S, Karunamurthy T. Temperature-Aware X-filling for Very Large Scale Integrated Circuits. Gazi University Journal of Science. 2019;32(2):572-80.