Year 2018, Volume 5, Issue 1, Pages 44 - 55 2018-04-05

Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction

Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction

Daniel Katz Bonello [1] , Yuzo Iano [2] , Umberto Bonello Neto [3]

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With the constant demand of automotive industries for embedded electronic devices in order to employ them in vehicles that needs constant monitoring and management of their energy systems, analog voltmeters stands out in this kind of application by their measurement efficiency and driver’s assistance. This electronic device is often used for variable’s controlling in fields where requires total measurement preciosion, such as: automotive ebedded systems,  process control, electrical machenary testing, electronic diagnosis and so on. The current work was designed to the development of an analog voltmeter PCB’s design layout based on DFMEA (Design Failure Mode and Effects Analysis) methodology, to avoid potential failures during design conception. The confection process of those PCB’s layouts begins with the analysis of two original circuits in AutoCAD, where the main problem verifyed was the alterations to be done in the circuits due the layer’s distribution scenario. This problem was solved through SMT components re-adjustment applying DFMEA methodology. In the application of this meyhodology, the percentage of  potential failures was about to 61% to the first circuit and 38% to the second circuit. This results idicates that the application of DFMEA in PCB’s design layout is highly efficient to detect, identify and classify the risk and severity of potential failures during the project development.              

Keywords- Vehicle electronics, embedded systems, DFMEA, PCB design, instrumentation, failure reduction

Vehicle electronics, embedded systems, DFMEA, PCB design, instrumentation
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Primary Language en
Subjects Engineering, Multidisciplinary
Journal Section Research Article
Authors

Author: Daniel Katz Bonello (Primary Author)
Institution: University of Campinas
Country: Brazil


Author: Yuzo Iano
Institution: University of Campinas
Country: Brazil


Author: Umberto Bonello Neto
Institution: University of Campinas
Country: Brazil


Bibtex @research article { ijeat409405, journal = {International Journal of Energy Applications and Technologies}, issn = {}, eissn = {2548-060X}, address = {İlker ÖRS}, year = {2018}, volume = {5}, pages = {44 - 55}, doi = {10.31593/ijeat.409405}, title = {Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction}, key = {cite}, author = {Bonello, Daniel and Iano, Yuzo and Neto, Umberto} }
APA Bonello, D , Iano, Y , Neto, U . (2018). Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction. International Journal of Energy Applications and Technologies, 5 (1), 44-55. DOI: 10.31593/ijeat.409405
MLA Bonello, D , Iano, Y , Neto, U . "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction". International Journal of Energy Applications and Technologies 5 (2018): 44-55 <http://dergipark.org.tr/ijeat/issue/36457/409405>
Chicago Bonello, D , Iano, Y , Neto, U . "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction". International Journal of Energy Applications and Technologies 5 (2018): 44-55
RIS TY - JOUR T1 - Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction AU - Daniel Katz Bonello , Yuzo Iano , Umberto Bonello Neto Y1 - 2018 PY - 2018 N1 - doi: 10.31593/ijeat.409405 DO - 10.31593/ijeat.409405 T2 - International Journal of Energy Applications and Technologies JF - Journal JO - JOR SP - 44 EP - 55 VL - 5 IS - 1 SN - -2548-060X M3 - doi: 10.31593/ijeat.409405 UR - https://doi.org/10.31593/ijeat.409405 Y2 - 2018 ER -
EndNote %0 International Journal of Energy Applications and Technologies Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction %A Daniel Katz Bonello , Yuzo Iano , Umberto Bonello Neto %T Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction %D 2018 %J International Journal of Energy Applications and Technologies %P -2548-060X %V 5 %N 1 %R doi: 10.31593/ijeat.409405 %U 10.31593/ijeat.409405
ISNAD Bonello, Daniel , Iano, Yuzo , Neto, Umberto . "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction". International Journal of Energy Applications and Technologies 5 / 1 (April 2018): 44-55. https://doi.org/10.31593/ijeat.409405