TY  - JOUR
T1  - A PERFORMANCE ANALYSIS OF CLASSIFIED BINARY ADDER ARCHITECTURES AND THE VHDL SIMULATIONS
AU  - Sertbaş, Ahmet
AU  - Özbey, R.selami
PY  - 2011
DA  - December
JF  - IU-Journal of Electrical & Electronics Engineering
PB  - İstanbul Üniversitesi-Cerrahpaşa
WT  - DergiPark
SN  - 1303-0914
SP  - 1025
EP  - 1030
VL  - 4
IS  - 1
LA  - en
AB  - In this paper, the four binary adder architectures belong to a different adder class are studied and compared with each other to analyse their performances. Comparisons include the unit-gate models for area and delay. As the performance measure, the product of the area and the delay is used. By a VHDL simulator, the adder structures are simulated to verify the functional correctness and to measure delay times
UR  - https://dergipark.org.tr/tr/pub/iujeee/issue//116717
L1  - https://dergipark.org.tr/tr/download/article-file/98968
ER  -