@article{article_213918, title={PERFORMANCE AND COST EVALUATIONS OF ADDERS USED IN FPGA-BASED SYSTEMS}, journal={Technological Applied Sciences}, volume={6}, pages={73–84}, year={2011}, DOI={10.12739/10.12739}, url={https://izlik.org/JA94FX22WZ}, author={Şahin, İbrahim and Çakıcı, Süleyman and Erdogmus, Pakize}, keywords={Binary adders, Cost, Performance, FPGA, VHDL,}, abstract={One important component of the most digital designs is binary adders which greatly affects the total performance of the designs. In the literature several different types of adders were proposed. In this study, performance and cost evaluations of five selected adders, two of which were generated using IP Core Generator and three of which were designed adders, were done on two selected FPGA chips. The results show that, the adders generated using the IP Core Generator with DSP48Es block are the best in most cases. Among the three non-generated adders, the carry select adder showed slightly better performance on average on both chips than others. On the other hand, in contrary to the expectations, it costs about the same amount of hardware with the other two. Another outcome of this study is that using larger Look-up Tables did not improve the costs of the designed adders as much as expected.}, number={4}