TY  - JOUR
TT  - Design of a new BPSK modulator
AU  - Sönmez, Mehmet
AU  - Akbal, Ayhan
PY  - 2017
DA  - October
JF  - Pamukkale Üniversitesi Mühendislik Bilimleri Dergisi
PB  - Pamukkale Üniversitesi
WT  - DergiPark
SN  - 2147-5881
SP  - 492
EP  - 496
VL  - 23
IS  - 5
KW  - FPGA
KW  - RAM bit kullanımı
KW  - BPSK
N2  - In recently, the design of modulator algorithmsfor wireless communication systems by using digital circuits is widelyrealized. Moreover, it is crucial that resource utilization of the selectedalgorithm is reduced. In this paper, a modulator architecture which has lowerRAM bit that of conventional BPSK is proposed for BPSK (Binary Phase ShiftKeying) modulation technique that is used widely in wireless communicationsystems. The architecture can achieve to save RAM bit utilization by up to87.5% with respect to conventional BPSK. In addition, a real-time messagesignal is applied on ADC (Analog to Digital Converter) which is integrated on Altera DE-0 Nano FPGA(Field Programmable Gate Array) in the paper. It is shown that proposedstructure is practically realizable by achieving of message signal in output ofDAC (Digital to Analog Converter) after modulation and demodulation processes.
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UR  - https://dergipark.org.tr/tr/pub/pajes/issue//345299
L1  - https://dergipark.org.tr/tr/download/article-file/352590
ER  -