COMPARATIVE STUDY OF 0 . 18 ΜM LINEARIZED CMOS LOW NOISE AMPLIFIER

This paper presents a comparative study of linearization techniques for Complementary Metal Oxide Semiconductor low noise amplifier. The study is performed previously reported three different techniques; modified derivative superposition, post distortion and noise/distortion cancellation. To perform the design, cascade amplifier topology and 0.18μm Complementary Metal Oxide Semiconductor process parameters is used. These performance are studied in the frequency range of 1 GHz to 5 GHz through simulation. Simulations are performed in Applied Wave Research design environments program.The results are compared with each other and previously reported publication in ways of Input third order intercept point, Input second order intercept point, gain, input return loss, noise figure and DC power. Keywords— Complementary Metal Oxide Semiconductor,Low noise amplifier, linearization techniques.


Introduction
The low noise amplifier, as its name implies, is the first block after the loop in the receiver chain that amplifies weak signals without adding noise.There is less noise than other amplifiers.As is known from the Friis expression, the total system is the first layer of the dominant floor system, which determines the sensitivity of reception because of the noises [1].
Therefore, when adding a small amount of noise to a low noise amplifying system, high gain is required, low power consumption and high sensitivity must be maintained.At the same time, it should suppress distortion for good linearity and have a fixed 50Ω input and output impedance value for maximum power transmission.Providing high linearity is achieved by improving the third-order intersection point (IIP3) of the amplifier.However, in order to achieve all these desired properties, the linearization techniques must be simple and should not adversely affect the noise and the gain at the same time [2].
In this paper, low-noise amplifier design was implemented using three methods: derivative superposition, noise / distortion cancellation, and post distortion.In order to obtain the simulation results, the appropriate low-noise amplifier topology was chosen in the first step.By applying each technique to the selected topology, desired low noise amplifiers were created.The circuits were optimized and the appropriate values of the circuit elements were selected.Later, in order to provide impedance matching in the circuits, appropriate impedance circuits were established and the final state of the circuits was obtained and the analysis results were obtained.0.18um CMOS (Complementary Metal Oxide Semiconductor) parameters are used in the operation.Power gains (S21), input impedance matching (S11) and noise factors were found with the help of the s parameters of each of the techniques.IIP3 (Input third order intercept point) performance was measured using a dual tone test simulation.
As for the organization of the paper, Section 2 discusses the architecture of the linearization techniques and linearized LNA's (low noise amplifier).Section 3 show the simulation result and findings.In section 4, the results of the simulation results are compared with previous studies and with each other in terms of linearity, noise, impedance matching and gain.

Linearization Techniques and Circuit Designs
The improved derivative superposition technique is seen as a special case of the feed forward technique.With this technique, an amplifier design can be realized in which the third order interference is very low.It is a technique based on the working of the transistors in the circuit in different regions.The reason why this technique is called the "derivative superposition" is to add the third derivative (g3) of the drain current of the main and auxiliary transistor to destroy the distortion.Figure 1(a) shows the circuit connection for the MDS (modified derivative superposition) technique.Where Ma is the main transistor and Mb is the auxiliary transistor [5].
As shown in Figure 1(b), similar to the derivative superposition technique, the post distortion technique (PD) utilizes the nonlinearity of the auxiliary transistor to remove the nonlinearity of the main element, but this technique has been developed from two aspects: 1) The auxiliary transistor is connected to the output of the main element instead of being directly connected to the input to minimize the effect of input matching.
2) The operation of all transistors in saturation provides better linearity [6].
Noise / distortion cancellation, CG (MA) and CS (MB) parallel transistors are shown in Figure 1c.This circuit is realized by the supply voltage in the "IN" node.The nonlinearity of MA can be modeled as a source of current between drainage and source controlled by Vgs and Vds.Thus, the thermal noise and distortion of both channels flowing through the CG and CS paths of the MA are removed from the output when the signal is added.Noise / distortion cancellation requires Vx = Vy equality [7].
(2) (3) The cascaded amplifiers provide high power gain, good noise performance, low consumption and high reverse isolation.But, the stacking of transistors in this LNA limits the available voltage hedroom.The limitation can be overcome by use of folded cascode topology.
The proposed cascade amplifier and the improved derivative superposition circuit, shown in Figure 2, are conveniently connected to form a low noise amplifying circuit.The working logic of the improved derivative superposition is to operate the transistors in different regions.Accordingly, while the main transistor is operated in the saturation region, the auxiliary transistor is biased in the weaker inversion region.The LC tank is used to set the frequency range that the operation is running.In post distortion method, similar to the derivative superposition method, the non-linearity of the auxiliary transistor is utilized in order to eliminate the nonlinearity of the element.To minimize the effect of input matching, the auxiliary transistor is connected directly to the output of the main element instead of being connected to the input.In addition, all of the transistors are operated in saturate mode to provide better linearity.The circuit is supplied with 0.8V voltage.The circuit diagram of the post distortion method is shown in Figure 3.

Figure 3. Linearized LNA with Post Distortion
In the noise/distortion cancellation technique, cascade low noise amplifying topology is used as in the post distortion technique.After setting the desired low noise amplifying circuit with the selected topology, the circuit element values were selected by optimization.In Figure 4, the circuit diagram of the noise cancellation circuit is given.

Measurement Results
The implementation of this method has been carried out at specific stages.First, the desired lownoise amplifier topology is selected.Due to its advantages such as high gain, good noise performance and low power consumption, cascade low noise amplifier topology is used.It is known that the traditional derivative superposition worsens the decay from the second level while improving the third decay.Because of this disadvantage, the modified derivative superposition method which improves the IIP3 value without damaging the IIP2 (Input second order intercept point) value is preferred.This method also minimizes the feedback from the source to the door.For this reason, after the appropriate topology has been determined, the modified superposition method is applied to the circuit and a new low-noise amplifier circuit is created.In Figure 5a, the gain, S11 and noise curves of the MDS technique are given.According to this, it is seen that the gain value is 8,934 dB, S11 value is -10,53 dB and the noise factor is 1,921 dB.The IIP2 curve is shown in Figure 5b and the IIP3 curve is shown in Figure 5c.These graphs show the linearity of the system.According to these graphs, IIP2 value is -15,071 dBm and IIP3 value is -14,47 dBm.Numerical results.The results of the analysis of the low noise amplifier circuit generated by the post distortion technique are given.When we look at these results in general, it is seen that the second and third degree intercept values are in average values.Accordingly, the IIP2 value did not damage the IIP2 value while recovering.It has been seen that the circuit is added to the noisy minimum levels and high gain value is obtained.
In figure 6(a), curves of gain, S11 and noise values of the linearized LNA by the post distortion method are given.For gain 3 GHz frequency and for S11 and noise factor minimum points on the curve are selected.According to this results, it is seen that the gain value is 20,913 dB, the noise factor is 1,569 dB and S11 value is -13,9 dB.Figures 6b and 6c show the IIP2 and IIP3 values of the amplifier circuit.While previous techniques only compensate gm's nonlinearity, noise/distortion technique can remove all structural distortions generated by the main transistor, including non-linearity of gm and gds.After the distortion of the main transistor is removed, the distortion of the auxiliary transistor no longer suppresses the nonlinearity, which creates two terms: 1) Structural third-order distortion of the auxiliary transistor.
2) Second-order interaction from the CG-CS cascade.Operating the optimal or complementary TS of the auxiliary transistor improves the linearity.

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The traditional derivative superposition method usually worsens degradation from the second order when improving the third order intercept point.Thus, the improved derivative superposition method is preferred.And, as a result of this application, is seen that in Table 1, IIP2 and IIP3 values are much better than the post distortion and noise / distortion cancellation methods.Besides, it is seen that the gain are lower than other methods.Input impedance loss and DC power consumption are average values.In order to achieve better linearity in the post distortion method, all transistors are operated in saturation region.And when the results are examined, it is seen that in Table 2, post distortion method has a lower noise figure than the other methods.The input impedance loss, IIP2, IIP3 and DC power consumption are average values when a relatively good gain is seen.In noise/distortion cancellation method, higher gains are achieved compared to other methods.In addition, an ideal input impedance loss is achieved and very low DC power consumption is achieved.However, the noise level in the circuit is above the expected value and is not observed in the ideal values when compared with other methods.In addition, IIP2 and IIP3 are average values according to the previous studies and are lower than other methods.
As a result, in general, it can be seen that in Table 4 in the modified derivative method with the best performance of IIP2 and IIP3, the lowest noise addition to the circuit is achieved in the post distortion method and the highest gain is obtained by noise / distortion cancellation method.It is seen that these results are supported when the previously made and comparative sources and publications are examined.In future work, this work is expanded to include new linearization techniques for designing a more ideal low-noise amplifier.In addition to this, it is planned to use the AWR (Applied Wave Research).
Design Environment program to implement and apply the low noise amplifier model.In this way, it is possible to compare the simulation results obtained with the application results and make a more accurate interpretation.