ij3dptdi International Journal of 3D Printing Technologies and Digital Industry 2602-3350 2602-3350 Kerim ÇETİNKAYA 10.46519/ij3dptdi.1856787 Evolutionary Computation Satisfiability and Optimisation Artificial Intelligence (Other) Evrimsel Hesaplama Memnuniyet ve Optimizasyon Yapay Zeka (Diğer) IMPLEMENTATION OF GENETIC ALGORITHM ACCELERATOR ON FPGA FOR TRAVELING SALESMAN PROBLEM AND PERFORMING COMPARATIVE PERFORMANCE ANALYSIS IMPLEMENTATION OF GENETIC ALGORITHM ACCELERATOR ON FPGA FOR TRAVELING SALESMAN PROBLEM AND PERFORMING COMPARATIVE PERFORMANCE ANALYSIS https://orcid.org/0000-0002-1326-4537 Kumral Cem Deniz ISPARTA UYGULAMALI BİLİMLER ÜNİVERSİTESİ 04 30 2026 10 1 176 191 01 05 2026 03 15 2026 Copyright © 2017, International Journal of 3D Printing Technologies and Digital Industry 2017 International Journal of 3D Printing Technologies and Digital Industry

The primary objective of this study is to perform a comprehensive comparative performance analysis between traditional processor-based systems and hardware-oriented architectures for solving the Traveling Salesman Problem (TSP). On this way, a high-performance and scalable Genetic Algorithm (GA) accelerator was designed and implemented on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA) using VHSIC Hardware Description Language (VHDL). The proposed architecture employs a Dual-Port Block RAM (BRAM) structure and a 4-stage parallel pipeline to overcome the computational bottlenecks and memory access latencies inherent in serial Central Processing Units (CPU) execution. The performance of the developed system was benchmarked against a Python-based CPU implementation using TSPLIB datasets. Experimental results reveal that the FPGA-based accelerator provides a big advantage, achieving a speedup ratio of up to 121.24x on used datasets. This comparative analysis demonstrates that the proposed hardware-based approach offers a superior, cost-effective, and deterministic alternative to software-based solutions for real-time optimization and Edge AI applications.

The primary objective of this study is to perform a comprehensive comparative performance analysis between traditional processor-based systems and hardware-oriented architectures for solving the Traveling Salesman Problem (TSP). On this way, a high-performance and scalable Genetic Algorithm (GA) accelerator was designed and implemented on a Xilinx Artix-7 Field-Programmable Gate Array (FPGA) using VHSIC Hardware Description Language (VHDL). The proposed architecture employs a Dual-Port Block RAM (BRAM) structure and a 4-stage parallel pipeline to overcome the computational bottlenecks and memory access latencies inherent in serial Central Processing Units (CPU) execution. The performance of the developed system was benchmarked against a Python-based CPU implementation using TSPLIB datasets. Experimental results reveal that the FPGA-based accelerator provides a big advantage, achieving a speedup ratio of up to 121.24x on used datasets. This comparative analysis demonstrates that the proposed hardware-based approach offers a superior, cost-effective, and deterministic alternative to software-based solutions for real-time optimization and Edge AI applications.

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