Direct Digital Frequency Synthesizer Designs in MATLAB
Abstract
This study presents the structure of the Direct Digital Frequency Synthesizers (DDFSs) which have several advantages compared to conventional synthesizers such as high frequency, fast switching speed and low power dissipations. In order to lessen the physical area and power dissipation, ROM compression techniques are applied in designs. Bipartite Table Method (BTM) and Multipartite Table Method (MTM) are utilized in this study because of the fact that they provide high compression rates. By using MTM, the compression rates of 157.54:1, 726.71:1 and 3463.29:1 are obtained at 58.40 dB, 75.30 dB and 84.66 dB SFDR levels, respectively.
Keywords
References
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Details
Primary Language
English
Subjects
Engineering
Journal Section
Conference Paper
Publication Date
December 1, 2016
Submission Date
November 30, 2016
Acceptance Date
December 1, 2016
Published in Issue
Year 2016 Number: Special Issue-1
Cited By
Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology
Journal of Circuits, Systems and Computers
https://doi.org/10.1142/S0218126622501936