A Secure Logic Locking Integration Technique for AES Algorithm

Priyadharshini M; Saravanan P

doi:10.55859/ijiss.1795996

A Secure Logic Locking Integration Technique for AES Algorithm

Abstract

The globalization of semiconductor manufacturing has increased vulnerabilities such as hardware Trojan insertion, overbuilding, reverse engineering, and intellectual property piracy. Logic locking has emerged as an effective countermeasure to protect integrated circuits using secret key activation. The Advanced Encryption Standard (AES) is widely deployed in Internet of Things (IoT) systems and therefore requires robust hardware-level protection. This work presents an architecture-level integration of Random Logic Locking and an Anti-SAT block within an AES encryption core implemented on an Artix-7 FPGA. Unlike prior studies that primarily evaluate Anti-SAT on benchmark circuits, the proposed approach embeds the locking framework directly into a complete cryptographic datapath and analyzes both hardware overhead and security characteristics. The design is evaluated in terms of area, power, throughput, Hamming distance corruptibility, and Satisfiability Checking(SAT) attack resilience. Experimental results demonstrate approximately 50\% output corruption under incorrect keys and incorrect key convergence during SAT attack attempts across multiple key sizes. The results indicate that the proposed integration enhances SAT attack resistance while maintaining acceptable hardware overhead, making it suitable for secure IoT hardware deployments.

Keywords

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Details

Primary Language

English

Subjects

Hardware Security

Journal Section

Research Article

Authors

Priyadharshini M ^*
0000-0001-6378-7478
India

Saravanan P
0000-0003-0785-807X
India

Publication Date

September 30, 2026

Submission Date

October 3, 2025

Acceptance Date

July 31, 2026

Published in Issue

Year 2026 Volume: 15 Number: 3

DOI

https://doi.org/10.55859/ijiss.1795996

IZ

https://izlik.org/JA57SY43HE

Cite

RIS / Bibtex

APA

M, P., & P, S. (2026). A Secure Logic Locking Integration Technique for AES Algorithm. International Journal of Information Security Science, 15(3), 1-17. https://doi.org/10.55859/ijiss.1795996

AMA

1.M P, P S. A Secure Logic Locking Integration Technique for AES Algorithm. IJISS. 2026;15(3):1-17. doi:10.55859/ijiss.1795996

Chicago

M, Priyadharshini, and Saravanan P. 2026. “A Secure Logic Locking Integration Technique for AES Algorithm”. International Journal of Information Security Science 15 (3): 1-17. https://doi.org/10.55859/ijiss.1795996.

EndNote

M P, P S (September 1, 2026) A Secure Logic Locking Integration Technique for AES Algorithm. International Journal of Information Security Science 15 3 1–17.

IEEE

[1]P. M and S. P, “A Secure Logic Locking Integration Technique for AES Algorithm”, IJISS, vol. 15, no. 3, pp. 1–17, Sept. 2026, doi: 10.55859/ijiss.1795996.

ISNAD

M, Priyadharshini - P, Saravanan. “A Secure Logic Locking Integration Technique for AES Algorithm”. International Journal of Information Security Science 15/3 (September 1, 2026): 1-17. https://doi.org/10.55859/ijiss.1795996.

JAMA

1.M P, P S. A Secure Logic Locking Integration Technique for AES Algorithm. IJISS. 2026;15:1–17.

MLA

M, Priyadharshini, and Saravanan P. “A Secure Logic Locking Integration Technique for AES Algorithm”. International Journal of Information Security Science, vol. 15, no. 3, Sept. 2026, pp. 1-17, doi:10.55859/ijiss.1795996.

Vancouver

1.Priyadharshini M, Saravanan P. A Secure Logic Locking Integration Technique for AES Algorithm. IJISS. 2026 Sep. 1;15(3):1-17. doi:10.55859/ijiss.1795996