Research Article

Redesign of Development Board for Engineering Education

Volume: 3 Number: 1 February 26, 2020
EN

Redesign of Development Board for Engineering Education

Abstract

With the rapid developments in technology, devices used in engineering applications are being renewed continuously. But sometimes this renewing process costs higher prices. For this reason there could be some delays at this point and this may cause a decrease in the quality of education. In this study, it is tried to find a solution to the problem of outdated devices used in electronics engineering education. A multi-layered and complex FPGA (Field Programmable Gate Array) development board has been transformed into a more simple and updateable form which is consisting of two layers. By this way, the development card can be easily adapted to the different projects needed in electronic engineering education.

Keywords

Thanks

Konya Teknik Üniversitesi

References

  1. Uzun, I. S., Amira, A. (2005). Design and FPGA Implementation of Finite Ridgelet Transform. IEEE International Symposium on Circuits and Systems-ISCAS 2005, Kobe-Japan, 5826-5829.
  2. Terasic Technologies Inc. (2007). Altera Cyclone IV Development & Education Board Schematics, 1-14.
  3. Terasic Technologies Inc. (2012). DE0-Nano User Manual, 4-150.
  4. Santarini, M. (2012). So Much More Than Gate Arrays. Xcell Journal. 81(4).
  5. Crookes, D., Benkrid, K., Bouridane, A., Alotaibi K., Benkrid, A. (2000). Design and Implementation of a High Level Programming Environment for FPGA Based Image Processing. IEEE Proceedings - Vision, Image and Signal Processing. 147(4), 377-384.
  6. Curry, M.P., Morgan, F., Kilmartin, L. (2001). Xilinx FPGA Implementation of an Image Classifier for Object Detection Applications. Int. Conf. on Image Processing-ICIP 2001. Thessaloniki-Greece. 346-349.
  7. Uzun, I.S., Amira, A., Bouridane, A. (2005). FPGA Implementations of Fast Fourier Transforms for Real-Time Signal and Image Processing. IEEE Int. Conf. on Field Programmable Technology -FPT 2005. Singapore. 284-296.
  8. Huitzil, C.T., Estrada, M.A. (2005). FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. EURASIP Journal on Applied Signal Processing. 7, 1024-1034.

Details

Primary Language

English

Subjects

Engineering

Journal Section

Research Article

Publication Date

February 26, 2020

Submission Date

February 24, 2020

Acceptance Date

February 26, 2020

Published in Issue

Year 2020 Volume: 3 Number: 1

APA
Erdoğan, K. (2020). Redesign of Development Board for Engineering Education. Scientific Journal of Mehmet Akif Ersoy University, 3(1), 15-19. https://izlik.org/JA35PL57PA
AMA
1.Erdoğan K. Redesign of Development Board for Engineering Education. Techno-Science. 2020;3(1):15-19. https://izlik.org/JA35PL57PA
Chicago
Erdoğan, Kemal. 2020. “Redesign of Development Board for Engineering Education”. Scientific Journal of Mehmet Akif Ersoy University 3 (1): 15-19. https://izlik.org/JA35PL57PA.
EndNote
Erdoğan K (February 1, 2020) Redesign of Development Board for Engineering Education. Scientific Journal of Mehmet Akif Ersoy University 3 1 15–19.
IEEE
[1]K. Erdoğan, “Redesign of Development Board for Engineering Education”, Techno-Science, vol. 3, no. 1, pp. 15–19, Feb. 2020, [Online]. Available: https://izlik.org/JA35PL57PA
ISNAD
Erdoğan, Kemal. “Redesign of Development Board for Engineering Education”. Scientific Journal of Mehmet Akif Ersoy University 3/1 (February 1, 2020): 15-19. https://izlik.org/JA35PL57PA.
JAMA
1.Erdoğan K. Redesign of Development Board for Engineering Education. Techno-Science. 2020;3:15–19.
MLA
Erdoğan, Kemal. “Redesign of Development Board for Engineering Education”. Scientific Journal of Mehmet Akif Ersoy University, vol. 3, no. 1, Feb. 2020, pp. 15-19, https://izlik.org/JA35PL57PA.
Vancouver
1.Kemal Erdoğan. Redesign of Development Board for Engineering Education. Techno-Science [Internet]. 2020 Feb. 1;3(1):15-9. Available from: https://izlik.org/JA35PL57PA