Design and Development of ONOFIC-Enhanced FinFET and CNTFET-Based Nano Domino Circuits for Subthreshold Leakage Reduction

Year 2026, Volume: 10 Issue: 1, 164 - 177, 16.12.2025

Ramavathu Ramesh Naik , D Ramakrishna Reddy , Dr Krishnanaik Vankdoth

https://izlik.org/JA99MW75DG

Abstract

Improving energy efficiency is paramount in today’s nano-scale VLSI systems, particularly for battery-powered and portable electronic devices. This research presents a novel design methodology for low-leakage domino logic circuits utilizing FinFET and CNTFET technologies at the 32nm technology node. The primary objective is to mitigate subthreshold leakage power without sacrificing performance or area efficiency. Four innovative circuit architectures based on the ONOFIC (ON/OFF Isolation Control) technique are proposed: (i) ONOFIC Pull-Down, (ii) Dual-ONOFIC Pull-Down, (iii) ONOFIC Pull-Up, and (iv) Sandwiched ONOFIC structure. These designs strategically isolate dynamic nodes from the evaluation network to reduce leakage during idle states. Additionally, dual-chirality CNTFET designs and LECTOR-based implementations are explored for comparative analysis. All circuits are simulated using the HSPICE tool, focusing on wide OR gates and extended to functional units such as multiplexers. Results demonstrate that the ONOFIC Pull-Up architecture offers the most effective leakage reduction, achieving 21.9% improvement over conventional footer-less domino logic and 69.5% over LECTOR-based domino circuits. The proposed nano-domino circuits provide a scalable, energy-efficient solution for advanced digital systems, including IoT edge devices and low-power processors

Keywords

FinFET , CNTFET , ONOFIC , subthreshold leakage , nano domino circuits

Ethical Statement

The research presented in this paper, titled "Design and Development of ONOFIC-Enhanced FinFET and CNTFET-Based Nano Domino Circuits for Subthreshold Leakage Reduction," adheres to ethical standards in research and publication. Originality and Plagiarism: This work is original and has not been submitted for publication elsewhere. All sources, references, and previously published work have been properly cited in accordance with academic standards. Data Integrity: All data and results presented in this study are authentic and accurately reflect the outcomes of the experiments conducted. The analysis and findings have been reported truthfully, with no manipulation of data to support preconceived conclusions. Conflict of Interest: The authors declare no conflicts of interest related to the research or publication of this paper. Human and Animal Rights: This research does not involve any human or animal subjects. The work is entirely focused on computational simulations and theoretical analysis in the domain of nanoelectronics. Ethical Responsibility: The authors acknowledge their responsibility to ensure the integrity and quality of their work. All research activities were conducted in accordance with relevant ethical guidelines and standards for academic research.

Supporting Institution

Chaitanya Deemed to be University, Hyderabad, Telangana, India

Project Number

1789379

Thanks

THANK YOU

References

• Kumar, S., et al. (2020). Leakage current analysis in CMOS domino circuits at 7 nm technology node. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(4), 915–924.
• Lee, J., & Kim, M. (2019). Power reduction in CMOS domino logic by adaptive body biasing. IEEE Journal of Solid-State Circuits, 54(2), 512–520.
• Gupta, & Singh, P. (2020). Subthreshold leakage minimization in dynamic logic circuits: A review. Microelectronics Journal, 97, 23–32.
• Zhang, M., et al. (2019). FinFET technology for low-power VLSI: Design and applications. IEEE Transactions on Electron Devices, 66(9), 3752–3759.
• Chen, Y., et al. (2020). Design of FinFET-based domino logic circuits for subthreshold leakage reduction. IEEE Transactions on Circuits and Systems I, 67(8), 2851–2860.
• Patel, R., & Bhattacharya, K. (2020). Threshold voltage control in FinFET domino logic for ultra-low power applications. Microelectronics Reliability, 105, 113–120.
• Huang, T., & Wang, L. (2021). Multi-fin FinFET domino logic for low leakage and high speed. IEEE Transactions on Nanotechnology, 19, 32–39.
• Roy, S., et al. (2021). Performance analysis of FinFET-based dynamic logic circuits. IEEE Transactions on Device and Materials Reliability, 21(3), 389–396.
• Singh, P., et al. (2021). Compact CNTFET model and its application in digital circuit design. IEEE Transactions on Electron Devices, 68(1), 300–308.
• Alam, M. R., et al. (2020). Carbon nanotube FETs for low-power high-speed digital circuits. IEEE Journal of the Electron Devices Society, 8, 148–157.
• Kim, N., & Lee, H. (2021). SPICE-compatible CNTFET model for nanoelectronic circuit design. IEEE Transactions on Circuits and Systems I, 68(4), 1391–1401.
• Kumar, V., et al. (2020). Logic design using CNTFETs: Modeling and simulation. Microelectronics Journal, 98, 45–53.
• Das, & Basu, S. (2021). CNTFET-based domino logic circuits for low power applications. IEEE Transactions on Nanotechnology, 19, 66–73.
• Zhao, H., et al. (2020). Design and analysis of CNTFET domino logic gates. IEEE Transactions on Electron Devices, 67(11), 4778–4784.
• Roy, K., et al. (2019). LECTOR: A technique for leakage reduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1), 108–116.
• Wang, L., & Zhang, J. (2019). Footer logic-based leakage reduction in dynamic circuits. Microelectronics Journal, 95, 51–58.
• Lee, Y., et al. (2020). Stacking effect for leakage control in nanoscale CMOS. IEEE Transactions on Electron Devices, 67(3), 1241–1247.
• Choi, D., & Kang, M. (2021). Leakage reduction in FinFET circuits using device and circuit-level techniques. IEEE Transactions on Nanotechnology, 19, 22–29.
• Patel, J., et al. (2020). Evaluation of leakage reduction techniques in CNTFET-based circuits. IEEE Transactions on Electron Devices, 67(8), 3381–3388.
• Narayan, S., & Mehta, R. (2020). Variability and leakage challenges in nanoscale domino circuits. Microelectronics Reliability, 110, 113715.
• Zhang, F., & Liu, X. (2020). Dynamic node leakage and charge sharing in nano-domino circuits. IEEE Transactions on Circuits and Systems II, 67(12), 3010–3015. Singh, et al. (2021). Low power nano-domino logic with leakage control for future technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 29(2), 314–323.
• Gupta, & Roy, S. (2021). Advanced leakage suppression techniques in FinFET circuits. IEEE Journal of the Electron Devices Society, 9, 108–116.
• Chatterjee, M., et al. (2021). CNTFET-based circuits for low-power applications: A review. Microelectronics Journal, 108, 104800.
• Singh, P., et al. (2021). Design challenges in low-power CNTFET-based domino logic. IEEE Transactions on Nanotechnology, 20, 123–130.
• Liu, T., & Chen, H. (2022). Process variation impact on FinFET domino logic. IEEE Transactions on Device and Materials Reliability, 22(1), 91–98.
• Kumar, S., & Sinha, A. (2021). Low power dynamic logic design using leakage reduction techniques. Microelectronics Journal, 111, 105001.
• Banerjee, R., et al. (2021). Integrated device-circuit approaches for leakage control in nanoelectronics. IEEE Transactions on Electron Devices, 68(9), 4553–4561.
• Zhao, J., & Wang, L. (2022). High-performance CNTFET domino logic with leakage reduction. IEEE Transactions on Circuits and Systems I, 69(3), 876–883.
• Verma, K., et al. (2021). Comprehensive analysis of leakage current mechanisms in nano-scale domino circuits. Microelectronics Journal, 109, 104758.