Design and implementation of Area and Power efficient reconfigurable FIR filter with low complexity coefficients

Yıl 2019, Cilt: 32 Sayı: 2, 494 - 507, 01.06.2019

Sridevi Sriadibhatla Killadi Baboji

Öz

This paper presents the
design and implementation of area and power efficient reconfigurable finite
impulse response (FIR) filter. We present a method for designing a
reconfigurable filter with low binary complexity coefficients (LBCC) and thus
to optimize the filter while satisfying the design specifications. The total
number of non zero binary bits is taken as a measure of the binary complexity
(BC) of a coefficient. We propose two implementation architectures namely
signed-magnitude architecture (SMA) and signed-decimal architecture (SDA) which
are based on 3-bit binary common sub expression elimination (BCSE) algorithm
and vertical horizontal BCSE (VHBCSE) algorithm respectively. SMA and SDA
reduce the redundant computations of the coefficient multiplications in the
filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The
synthesis results show that the proposed filters are area and power efficient
when compared with the existing ones.

Anahtar Kelimeler

Reconfigurable FIR filter; BCSE algorithm; VHBCSE algorithm; Binary complexity.

Kaynakça

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