Design and implementation of Area and Power efficient reconfigurable FIR filter with low complexity coefficients

Year 2019, Volume: 32 Issue: 2, 494 - 507, 01.06.2019

Sridevi Sriadibhatla , Killadi Baboji

Abstract

This paper presents the
design and implementation of area and power efficient reconfigurable finite
impulse response (FIR) filter. We present a method for designing a
reconfigurable filter with low binary complexity coefficients (LBCC) and thus
to optimize the filter while satisfying the design specifications. The total
number of non zero binary bits is taken as a measure of the binary complexity
(BC) of a coefficient. We propose two implementation architectures namely
signed-magnitude architecture (SMA) and signed-decimal architecture (SDA) which
are based on 3-bit binary common sub expression elimination (BCSE) algorithm
and vertical horizontal BCSE (VHBCSE) algorithm respectively. SMA and SDA
reduce the redundant computations of the coefficient multiplications in the
filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The
synthesis results show that the proposed filters are area and power efficient
when compared with the existing ones.

Keywords

Reconfigurable FIR filter; BCSE algorithm; VHBCSE algorithm; Binary complexity.

References

• [1] Hentschel, T. and Fettweis, G., “Software radio receivers”, CDMA techniques for third generation mobile systems. , Springer, Boston, MA, 257-283, (1999).
• [2] Hentschel, T., Henker, M. and Fettweis, G., “The digital front-end of software radio terminals”, IEEE Personal communications. , 6(4): 40-46, (1999).
• [3] Dillinger, M., Madani, K. and Alonistioti, N., Software defined radio: Architectures, systems and functions. , John Wiley & Sons, (2005).
• [4] Singhal, S. K. and Mohanty, B. K., “Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic”, Journal of Circuits, Systems and Computers. , 25(07): 1650073, (2016).
• [5] Hu, J., Huang, Z., Liu, C., Su, S. and Zhou, J., “Design of Digital Channelizer Based on Source Number Estimation”, Journal of Circuits, Systems and Computers, 25(02): 1650008. (2016).
• [6] Hewlitt, R.M. and Swartzlantler, E.S., “Canonical signed digit representation for FIR digital filters”, In Signal Processing Systems, 2000. , SiPS 2000. 2000 IEEE Workshop on (pp. 416-426). IEEE. (2000).
• [7] Hashemian, R., “A new method for conversion of a 2's complement to canonic signed digit number system and its representation”, In Signals, Systems and Computers, 1996. , Conference Record of the Thirtieth Asilomar Conference on: (pp. 904-907). IEEE. November. (1996). [8] He, S. and Torkelson, M., “FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers”, In Custom Integrated Circuits Conference, 1994. , Proceedings of the IEEE 1994: 81-84. IEEE. May. (1994).
• [9] Chen, K.H. and Chiueh, T.D., “A low-power digit-based reconfigurable FIR filter”, IEEE Transactions on Circuits and Systems II: Express Briefs. , 53(8): 617-621, (2006).
• [10] Tang, Z., Zhang, J. and Min, H., “A high-speed, programmable, CSD coefficient FIR filter”, IEEE Transactions on Consumer Electronics. , 48(4): 834-837, (2002).
• [11] Muhammad, K. and Roy, K., “Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. , 10(3): 292-300, (2002).
• [12] Park, J., Jeong, W., Mahmoodi-Meimand, H., Wang, Y., Choo, H. and Roy, K., “Computation sharing programmable FIR filter for low-power and high-performance applications”, IEEE Journal of solid-state Circuits. , 39(2): 348-357, (2004).
• [13] Voronenko, Y. and Püschel, M., “Multiplierless multiple constant multiplication”, ACM Transactions on Algorithms (TALG). , 3(2): 11, (2007).
• [14] Gustafsson, O. and Dempster, A.G., “On the use of multiple constant multiplication in polyphase FIR filters and filter banks”, In under review to Nordic Signal Processing Symposium. , Espoo, Finland. June. (2004).
• [15] Mahesh, R. and Vinod, A.P., “New reconfigurable architectures for implementing FIR filters with low complexity”, IEEE transactions on computer-aided design of integrated circuits and systems. , 29(2): 275-288, (2010).
• [16] Hatai, I., Chakrabarti, I. and Banerjee, S., “An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation”, IEEE Transactions on very large scale integration (VLSI) systems. , 23(6): 1150-1154, (2015).
• [17] Hatai, I., Chakrabarti, I. and Banerjee, S., “An efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination algorithm for reconfigurable FIR filter synthesis”, IEEE Transactions on Circuits and Systems I: Regular Papers. , 62(4): 1071-1080, (2015).
• [18] Skaf, J. and Boyd, S.P., “Filter design with low complexity coefficients”, IEEE Transactions on Signal processing. , 56(7): 3162-3169, (2008).
• [19] Boyd, S. and Vandenberghe, L., Convex optimization. , Cambridge university press, (2004).