Synchronization of Fractional Order Chaotic Systems with Time Delay and FPGA Implementation

Year 2024, , 672 - 682, 15.07.2024

Semih Can Değirmen Kenan Altun

https://doi.org/10.34248/bsengineering.1486545

Abstract

It is very important to be able to express it mathematically for the control and development of electronic-based systems and the detection of many operating errors. It makes it easier to detect many problems in systems that can be expressed mathematically, as well as to be developed. In particular, studies on communication systems and the mathematical modeling and development of carrier signals and communication protocols in these systems have been increasing recently. The reliability of information signals has been increased by using chaotic-based systems, which attract attention with their complex structure, in communication systems. However, full-degree modeling of chaotic systems increases the number of erroneous bits, especially in the communication systems in which it is used, and causes long synchronization times due to time delays. For this reason, in addition to modeling chaotic systems in fractional order, it is necessary to take into account the time delays between the systems in order to synchronize the transmitter-receiver systems in the shortest possible time. In this study, it is aimed to obtain a chaotic system used in communication systems in fractional order, and then to reduce synchronization delays due to time delays with a controller. In the study, a fractional order chaotic system was designed using the Charef approximation method and the synchronization time due to time delays was reduced with a fuzzy logic-based controller. As a result, it is shown that the synchronization times of a chaotic system, where real system behavior is obtained in fractional order, can be reduced with a controller. The study was first implemented and verified experimentally using computer simulation and then using FPGA.

Keywords

Fractional order chaotic systems, Time delay systems, Charef method, FPGA

Ethical Statement

Bu araştırmada hayvanlar ve insanlar üzerinde herhangi bir çalışma yapılmadığı için etik kurul onayı alınmamıştır.

Supporting Institution

Türkiye Bilimsel ve Teknolojik Araştırma Kurumu (TÜBİTAK)

Project Number

123E274

Thanks

Bu çalışma, Türkiye Bilimsel ve Teknolojik Araştırma Kurumu (TÜBİTAK) tarafından 123E274 Numaralı proje ile desteklenmiştir. Projeye verdiği destekten ötürü TÜBİTAK’a teşekkürlerimizi sunarız.

Zaman Gecikmeli Kesir Dereceli Kaotik Sistemlerin Senkronizasyonu ve FPGA Uygulaması

Abstract

Elektronik tabanlı sistemlerin kontrolü, geliştirilmesi ve birçok işletme hatasının tespiti için matematiksel olarak ifade edilebilmesi oldukça önemlidir. Matematiksel olarak ifade edilebilen sistemlerde, geliştirilebilmesinin yanında birçok problemin tespit edilmesini de kolaylaştırır. Özellikle haberleşme sistemleri ve bu sistemlerdeki taşıyıcı sinyallerin, haberleşme protokollerinin matematiksel modellenmeleri ve geliştirilmesi ile ilgili çalışmalar son dönemde artmaktadır. Özellikle karmaşık yapısı ile dikkat çeken kaotik tabanlı sistemlerin haberleşme sistemlerinde kullanılmasıyla bilgi sinyallerinin güvenilirliği artırılmıştır. Ancak kaotik sistemlerin tam dereceli olarak modellenmesi, özellikle kullanıldığı haberleşme sistemlerindeki hatalı bit sayılarını artırmakta ve zaman gecikmelerinden kaynaklı uzun senkronizasyon sürelerine neden olmaktadır. Bu nedenle kaotik sistemlerin kesir dereceli olarak modellenmesinin yanında verici-alıcı sitemlerin mümkün olan en kısa sürelerde senkronize olmaları için sistemler arasındaki zaman gecikmelerinin de dikkate alınması gereklidir. Bu çalışmada haberleşme sistemlerinde kullanılan kaotik bir sistemin kesir dereceli olarak elde edilmesi, daha sonra ise bir kontrolör ile zaman gecikmelerinden kaynaklı senkronizasyon gecikmelerinin azaltılması amaçlanmıştır. Yapılan çalışmada Charef yaklaşım metodu kullanılarak kesir dereceli kaotik sistem tasarımı yapılmış ve bulanık mantık tabanlı bir kontrolör ile zaman gecikme sürelerinden kaynaklı senkronizasyon süresi azaltılmıştır. Neticede, kesir dereceli olarak gerçek sistem davranışı elde edilen bir kaotik sitemin bir kontrolör ile senkronizasyon sürelerinin azaltılabildiği gösterilmektedir. Yapılan çalışma önce bilgisayar benzetimi ile daha sonra ise FPGA kullanılarak deneysel uygulaması gerçekleştirilmiş ve doğrulanmıştır.

Keywords

Kesir dereceli kaotik sistemler, Zaman gecikmeli sistemler, Charef metodu, FPGA

Project Number

123E274

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