TR
EN
CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding
Abstract
Computations related to intra prediction and transform in High Efficiency Video Coding are highly computational demanding, especially when multiple intra prediction modes have to be computed for block-based image encoding. In this paper, we propose a parallel CUDA implementation of HEVC intra frame prediction and integer transform operations on an embedded GPU platform. The presented implementation parallelizes HEVC intra prediction modes (35 in total, divided into planar, DC, and angular modes) and implements an efficient transform computation utilizing shared memory allocation. The proposed implementation was tested on NVIDIA Jetson Xavier NX platform using standardized test images and various quantization parameter settings. The results demonstrate that our solution accelerates the computations by up to 105.17× in terms of kernel computations compared to the sequential CPU implementation. Taking into account CPU–GPU memory transfer and synchronization overheads, the acceleration factor for the end-to-end process is 1.62×. In terms of the reconstructed image quality, there is a small decrease in the average PSNR value equal to about 0.65 dB. It is mainly caused by implementation-related differences in parallel computation, rounding, and quantization procedures. These results show that intra-frame prediction and transform stages in HEVC video codec can be efficiently parallelized using CUDA; however, there are still memory transfer and synchronization overheads limiting end-to-end performance. Our implementation can serve as a building block of a fast HEVC encoder but not as a full-fledged video encoder itself. Source code and dataset for this research are freely available on Zenodo with the DOI: https://doi.org/10.5281/zenodo.17286247.
Keywords
- HEVC intra prediction
- CUDA
- Integer DCT
- Embedded GPU
- Intra-frame image coding
- Block-based image compression
Ethical Statement
Ethics committee approval was not required for this study because of there was no study on animals or humans.
References
- Akman, A., & Cekli, S. (2023). Efficient 2D DCT architecture based on approximate compressors for image compression with HEVC intra-prediction. Journal of Real-Time Image Processing, 20(22). https://doi.org/10.1007/s11554-023-01261-3
- Bloch, A., Casale-Brunet, S., & Mattavelli, M. (2023). Design space exploration for partitioning dataflow programs on CPU + GPU heterogeneous systems. Journal of Signal Processing Systems, 95. 1219–1229. https://doi.org/10.1007/s11265-023-01884-6
- Bross, B., Han, W.-J., Sullivian, G. J., Ohm, J.-R., & Wiegand, T. (2023). High Efficiency Video Coding (HEVC) text specification draft 9. http://phenix.itsudparis.eu/jct/doc_end_user/current_document.php?id=6803 (accessed on 15 June 2023).
- Ghorpade, J., Parande, J., Kulkarni, M., & Bawaskar, A. (2012). GPGPU processing in CUDA architecture, arXiv preprint arXiv:1202.4347.
- Harris, M. (2019). How to optimize data transfers in CUDA C/C++. NVIDIA Developer Blog. https://devblogs.nvidia.com/how-optimize-data-transfers-cuda-cc/
- Imen, W., Amna. M., Fatma. B., Ezahra. S. F., & Masmoudi. N. (2022). Fast HEVC intra-CU decision partition algorithm with modified LeNet-5 and AlexNet. Signal. Image and Video Processing. 16(7). 1811–1819. https://doi.org/10.1007/s11760-022-02139-w
- James, R., Abo-Zahhad. M., Inoue, K., & Sayed, M. S. (2024). Performance evaluation of all intra Kvazaar and x265 HEVC encoders on embedded system NVIDIA Jetson platform. Journal of Real-Time Image Processing. 21(67). https://doi.org/10.1007/s11554-024-01429-5
- Jingjing, Y., & Kehua, J. (2019). A fast intra prediction algorithm with simplified prediction modes based on utilization rates. 2019 IEEE/ACIS 18th International Conference on Computer and Information Science (ICIS). 225–229. Beijing. China.
Details
Primary Language
English
Subjects
Signal Processing
Journal Section
Research Article
Publication Date
September 15, 2026
Submission Date
July 7, 2026
Acceptance Date
August 14, 2026
Published in Issue
Year 2026 Volume: 9 Number: 5
APA
Kaplan, M., & Akman, A. (2026). CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding. Black Sea Journal of Engineering and Science, 9(5), 2474-2481. https://doi.org/10.34248/bsengineering.1988909
AMA
1.Kaplan M, Akman A. CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding. BSJ Eng. Sci. 2026;9(5):2474-2481. doi:10.34248/bsengineering.1988909
Chicago
Kaplan, Mücahit, and Ali Akman. 2026. “CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding”. Black Sea Journal of Engineering and Science 9 (5): 2474-81. https://doi.org/10.34248/bsengineering.1988909.
EndNote
Kaplan M, Akman A (September 1, 2026) CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding. Black Sea Journal of Engineering and Science 9 5 2474–2481.
IEEE
[1]M. Kaplan and A. Akman, “CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding”, BSJ Eng. Sci., vol. 9, no. 5, pp. 2474–2481, Sept. 2026, doi: 10.34248/bsengineering.1988909.
ISNAD
Kaplan, Mücahit - Akman, Ali. “CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding”. Black Sea Journal of Engineering and Science 9/5 (September 1, 2026): 2474-2481. https://doi.org/10.34248/bsengineering.1988909.
JAMA
1.Kaplan M, Akman A. CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding. BSJ Eng. Sci. 2026;9:2474–2481.
MLA
Kaplan, Mücahit, and Ali Akman. “CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding”. Black Sea Journal of Engineering and Science, vol. 9, no. 5, Sept. 2026, pp. 2474-81, doi:10.34248/bsengineering.1988909.
Vancouver
1.Mücahit Kaplan, Ali Akman. CUDA-Based Parallel Intra Prediction and Transform Architecture for Hevc Intra-Frame Image Coding. BSJ Eng. Sci. 2026 Sep. 1;9(5):2474-81. doi:10.34248/bsengineering.1988909