Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation

Year 2018, Volume: 18 Issue: 1, 52 - 59, 23.02.2018

Burcu Özbay Serap Çekli

Abstract

A Viterbi decoder system
comprises a convolutional encoder and Viterbi decoder. In general, the code
words generated from the input series of convolutional encoder arrive at the
decoder through a noisy channel; however, the channel noise can cause
corruption of code words. The Viterbi decoder extracts the original input
message from the corrupted data using the Viterbi algorithm based on the
maximum likelihood principle. A Viterbi decoder mainly comprises four essential
units: a branch metrics unit, add-compare-select unit, path metrics unit, and
survivor-path memory unit. Related complex calculations are repeated in these
units at each clock cycle. In this study, a power- and area-efficient Viterbi
decoder architecture that also reduces the computational complexity is
proposed. Initially, a hard-decision Viterbi decoder system architecture design
for Very Large Scale Integration (VLSI) realization was fulfilled without any
further improvement to compare the performance of fundamental and improved
designs with respect to power consumption. The initial design constitutes an
essential base for the improved power- and area-efficient Viterbi decoder
architecture. The improvements were made to achieve the less complex and
power-efficient architectural system design. The performance of the proposed
architecture was tested by a fieldprogrammable gate array (FPGA) platform, and
the results have been reported. The architectural design is described using the
Verilog hardware description language for comparing the related tests and
performance of FPGA platform.

Keywords

Viterbi decoder architecture, FPGA implementation, forward error correction

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