Düşük Gerilim Evirici Uygulamalarında Kullanılan Paralel Bağlı MOSFET’ler için Aktif Kapı Sürme Devresi Tasarımı

Öz

Düşük gerilim evirici uygulamalarında çıkışa aktarılabilecek akım kapasitesini artırıp, yüksek güç seviyelerine ulaşabilmek adına paralel bağlı MOSFET’lerin kullanımı oldukça önemlidir. Bu çalışma kapsamında paralel bağlı MOSFET’lerin akım paylaşımlarını iyileştirmek için bir aktif kapı sürme devresi önerilerek tasarlanmıştır. Paralel bağlı MOSFET’lerin akım paylaşımlarını bozan etmenler ele alınarak benzetişim çalışmaları gerçekleştirilmiş ve sonuçlardan akım paylaşımını bozan birden fazla parametre olduğu görülmüştür. Akım paylaşımını iyileştirmek için literatürde verilen aktif ve pasif kapı sürme devreleri incelendikten sonra birden fazla parazitik parametrenin etkisini azaltacak, MOSFET’lerin akım paylaşımını iyileştirecek, sıcaklık ve akım geribeslemesi ile kontrol edilen yeni bir hibrit aktif kapı sürme algoritması önerilmiştir. Önerilen algoritma benzetişim sonuçlarıyla desteklendikten sonra deneysel çalışmalar için bir devre kartı tasarlanarak prototiplenmiştir. Laboratuvar ortamında çift darbe testi kullanılarak yapılan deneysel testlerin sonuçları karşılaştırmalı olarak verilerek önerilen algoritmanın etkinliği gösterilmiştir.

Anahtar Kelimeler

• Düşük gerilim evirici
• paralel bağlı MOSFET
• akım paylaşımı
• aktif kapı sürme devresi

An Active Gate Driver Circuit Design for Parallel Connected MOSFETs in Low Voltage Inverter Applications

Öz

The use of parallel-connected MOSFETs is crucial in low-voltage inverter applications to increase the current capacity that can be transferred to the output and achieve high power levels. In this paper, an active gate driver circuit is proposed and designed to improve the current sharing of parallel-connected MOSFETs. Simulation studies were conducted by addressing the factors that disrupt current sharing in parallel-connected MOSFETs, and the results indicate the presence of multiple parameters affecting current sharing. After examining the active and passive gate driver circuits given in the literature to improve current sharing, a new hybrid active gate driver algorithm controlled by temperature and current feedback is proposed to reduce the influence of multiple parasitic parameters and improve the current sharing of MOSFETs. Following validation of the proposed algorithm with simulation results a circuit board was designed and prototyped for experimental studies. The effectiveness of the proposed algorithm was demonstrated through comparative results of experimental tests performed using double pulse testing in a laboratory environment.

Anahtar Kelimeler

• Low voltage inverter
• parallel connected MOSFETs
• current sharing

Kaynakça

1. [1] Soni, L., & Kaur, A. (2023, December). Why Electric Vehicles Are the Future of Transportation. In 2023 IEEE International Conference on ICT in Business Industry & Government (ICTBIG) (pp. 1-6). IEEE.
2. [2] Pillot, C. (2013, November). Micro hybrid, HEV, P-HEV and EV market 2012–2025 impact on the battery business. In 2013 World Electric Vehicle Symposium and Exhibition (EVS27) (pp. 1-6). IEEE.
3. [3] Muehlfeld, O., Wittig, B., & Fuchs, F. W. (2011, August). Development of an optimized power section for a 5 kW low voltage traction inverter. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications (pp. 1-9). IEEE.
4. [4] Al-Hmoud, A., Ismail, A., & Zhao, Y. (2023, March). A high-density 200-kW all Silicon Carbide three-phase inverter for traction applications. In 2023 IEEE Applied Power Electronics Conference and Exposition (APEC) (pp. 3143-3146). IEEE.
5. [5] Musumeci, S., Scrimizzi, F., Fusillo, F., Bojoi, R., Longo, G., & Mistretta, C. (2019, July). Low voltage high current trench-gate MOSFET inverter for belt starter generator applications. In 2019 AEIT International Conference of Electrical and Electronic Technologies for Automotive (AEIT AUTOMOTIVE) (pp. 1-6). IEEE.
6. [6] Tahmaz, O., Bay, F., & Yazar, A. (2022, September). Double Pulse Test of the Paralleled Power MOSFETs in High Current 48V Inverter Design. In 2022 IEEE 20th International Power Electronics and Motion Control Conference (PEMC) (pp. 62-69). IEEE.
7. [7] Du, L., Du, X., Cao, H., Yang, H., & Mantooth, H. A. (2023, May). A Simple Gate Driver Design for SiC MOSFET Paralleled Operation. In 11th International Conference on Power Electronics and ECCE Asia (ICPE 2023-ECCE Asia) (pp. 2026-2031). IEEE.
8. [8] Infineon Technologies. (2021, May). Paralleling power MOSFETs in high current applications (Application Note, Version 1.1).

9. [9] Infineon Technologies. (2018, April). Paralleling MOSFETs in high-current LV drive applications (Application Note, Version 1.0).
10. [10] Nexperia. (2021, September). Paralleling power MOSFETs in high power applications (Application Note, Version 1.1).
11. [11] Raciti, A., Melito, M., Nania, M., & Montoro, G. (2018, September). Effects of the device parameters and circuit mismatches on the static and dynamic behavior of parallel connections of silicon carbide MOSFETs. In 2018 IEEE Energy Conversion Congress and Exposition (ECCE) (pp. 1846-1852). IEEE.
12. [12] ON Semiconductor. (2021, May). MOSFET paralleling in high-power applications (Application Note No. AND90108/D).
13. [13] Infineon. (2004, January 30). IRF530NPbF datasheet. Retrieved from https://www.infineon.com/dgdl/irf530npbf.pdf?fileId=5546d462533600a4015355e386b1199a
14. [14] Wen, Y., Yang, Y., & Gao, Y. (2020). Active gate driver for improving current sharing performance of paralleled high-power SiC MOSFET modules. IEEE Transactions on power electronics, 36(2), 1491-1505.
15. [15] Texas Instruments. (2017, March). Understanding the basics of gate driver circuits (Application Note No. SLUA618A).
16. [16] Rohde & Schwarz. (2021, March). Tips & tricks on double pulse testing (Application Note).
17. [17] Wang, T. W., Chen, L. C., Takamiya, M., & Chen, P. H. (2024). Active Gate Driver IC Integrating Gate Voltage Sensing Technique for SiC MOSFETs. IEEE Transactions on Power Electronics.
18. [18] Ling, Y., Zhao, Z., & Zhu, Y. (2020). A self-regulating gate driver for high-power IGBTs. IEEE Transactions on Power Electronics, 36(3), 3450-3461.
19. [19] Tanriverdi, O., & Yildirim, D. (2022). Independent closed loop control of di/dt and dv/dt for high power IGBTs. Turkish Journal of Electrical Engineering and Computer Sciences, 30(3), 487-501.
20. [20] Texas Instruments. (2020, April). Power MOSFET Gate Driver Bias Optimization (Appl. Note No. SLUA958).
21. [21] De Paula, W. J., Tavares, G. H. M., Soares, G. M., Almeida, P. S., & Braga, H. A. C. (2020). Switching losses prediction methods oriented to power MOSFETs–a review. IET Power Electronics, 13(14), 2960-2970.