Research Article

Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System

Volume: 6 Number: 2 March 15, 2026

Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System

Abstract

This paper presents an enhanced ONOFIC (ON/OFF Isolation Control) nano-domino logic framework implemented using 32 nm FinFET and CNTFET technologies for ultra-low leakage VLSI systems. The proposed ONOFIC technique employs feedback-controlled transistors to dynamically isolate leakage paths in the pull-up and pull-down networks, significantly reducing subthreshold leakage while preserving the high-speed characteristics of domino logic. Four ONOFIC-based architectures—Pull-Down, Dual-ONOFIC, Pull-Up, and Sandwiched ONOFIC—are designed and evaluated to investigate the trade-offs between leakage reduction, delay, and power consumption. In addition, an AI-assisted optimization approach is explored to automatically tune circuit parameters such as feedback bias and device sizing for improved leakage control and energy efficiency. HSPICE simulations using realistic FinFET and CNTFET models demonstrate up to 78% leakage reduction, approximately 45% total power savings, and 50–55% improvement in Power-Delay Product (PDP) compared with conventional domino logic techniques. The AI-optimized configurations further enhance leakage suppression and robustness under process-voltage-temperature (PVT) variations. These results confirm that combining ONOFIC-based leakage control with AI-assisted optimization provides an effective methodology for designing energy-efficient nano-scale VLSI systems suitable for modern low-power applications.

Keywords

Supporting Institution

Chaitanya Deemed to be University, Hyderabad, Telangana, India

References

  1. 1. Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305–327. https://doi.org/10.1109/JPROC.2002.808156
  2. 2. Hanchate, N., & Ranganathan, N. (2004). LECTOR: A technique for leakage reduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration Systems, 12(2), 196–205. https://doi.org/10.1109/TVLSI.2003.821547
  3. 3. Sharma, V. K., Pattanaik, M., & Raj, B. (2014). ONOFIC approach: Low power high speed nanoscale VLSI circuits design. International Journal of Electronics, 101(1), 61–73. https://doi.org/10.1080/00207217.2013.769186
  4. 4. Sharma, V. K., Pattanaik, M. (2016). Design of low leakage variability aware ONOFIC CMOS standard cell library. Journal of Circuits Systems and Computers, 25(11), 1650134. https://doi.org/10.1142/S0218126616501346
  5. 5. Sharma, V. K., Pattanaik, M., & Raj, B. (2015). INDEP approach for leakage reduction in nanoscale CMOS circuits. International Journal of Electronics, 102(2), 200–215. https://doi.org/10.1080/00207217.2014.896042
  6. 6. Narendra, S., De, V., Antoniadis, D., Chandrakasan, A., & Borkar, S. (2001). Scaling of stack effect and its application for leakage reduction. International Symposium on Low Power Electronics and Design. https://doi.org/10.1145/383082.383132
  7. 7. Agarwal, A., Roy, S., & Roy, K. (2006). Leakage power analysis and reduction for nanoscale circuits. IEEE Micro, 26(2), 68–80. https://doi.org/10.1109/MM.2006.36
  8. 8. Park, J. C., & Mooney, V. J. (2006). Sleepy stack leakage reduction. IEEE Transactions on VLSI Systems, 14(11), 1250–1263. https://doi.org/10.1109/TVLSI.2006.886398

Details

Primary Language

English

Subjects

Circuits and Systems, Engineering Electromagnetics

Journal Section

Research Article

Publication Date

March 15, 2026

Submission Date

September 5, 2025

Acceptance Date

March 5, 2026

Published in Issue

Year 2026 Volume: 6 Number: 2

APA
Naik, M. R. R., Donapati, D. R. R., & Vankdoth, D. K. (2026). Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System. Engineering Perspective, 6(2), 222-232. https://doi.org/10.64808/engineeringperspective.1771169
AMA
1.Naik MRR, Donapati DRR, Vankdoth DK. Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System. engineeringperspective. 2026;6(2):222-232. doi:10.64808/engineeringperspective.1771169
Chicago
Naik, Mr Ramavathu Ramesh, Dr Ramakrishna Reddy Donapati, and Dr Krishnanaik Vankdoth. 2026. “Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage With AI-Assisted Optimization in 32 Nm VLSI System”. Engineering Perspective 6 (2): 222-32. https://doi.org/10.64808/engineeringperspective.1771169.
EndNote
Naik MRR, Donapati DRR, Vankdoth DK (March 1, 2026) Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System. Engineering Perspective 6 2 222–232.
IEEE
[1]M. R. R. Naik, D. R. R. Donapati, and D. K. Vankdoth, “Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System”, engineeringperspective, vol. 6, no. 2, pp. 222–232, Mar. 2026, doi: 10.64808/engineeringperspective.1771169.
ISNAD
Naik, Mr Ramavathu Ramesh - Donapati, Dr Ramakrishna Reddy - Vankdoth, Dr Krishnanaik. “Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage With AI-Assisted Optimization in 32 Nm VLSI System”. Engineering Perspective 6/2 (March 1, 2026): 222-232. https://doi.org/10.64808/engineeringperspective.1771169.
JAMA
1.Naik MRR, Donapati DRR, Vankdoth DK. Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System. engineeringperspective. 2026;6:222–232.
MLA
Naik, Mr Ramavathu Ramesh, et al. “Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage With AI-Assisted Optimization in 32 Nm VLSI System”. Engineering Perspective, vol. 6, no. 2, Mar. 2026, pp. 222-3, doi:10.64808/engineeringperspective.1771169.
Vancouver
1.Mr Ramavathu Ramesh Naik, Dr Ramakrishna Reddy Donapati, Dr Krishnanaik Vankdoth. Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System. engineeringperspective. 2026 Mar. 1;6(2):222-3. doi:10.64808/engineeringperspective.1771169

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