A Low Area Fully Pipelined Implementation of JPEG on FPGA

Year 2018, Volume: 19 Issue: 3, 685 - 697, 01.09.2018

Atakan Doğan İsmail San

Abstract

This paper presents a low-area and high-throughput design and implementation of JPEG encoder on FPGA. The design consists of three main components: (1) 2-D DCT module, based on the row-column decomposition technique, (2) Quantization in zigzag ordering, based on look-up tables, and (3) Entropy coder, transforming the quantized DCT coefficients into JPEG words. All components are fully pipelined and optimized for FPGA resource utilization. The proposed implementation of JPEG encoder is able to encode 143 and 71 SDTV frames per second with 720x480 gray scale and color pixels per frame, respectively, on Xilinx Spartan 6 FPGA. Moreover, the proposed architecture is capable of encoding at least 53 and 26 HD Ready TV frames per second with 1280x720 gray scale and color pixels per frame, respectively, on this FPGA chip. Thus, the proposed JPEG encoder architecture is well-suited to various image and video compressing applications where performance and area are significantly important.

Keywords

JPEG compression, Discrete cosine transform, Logic design, FPGA

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