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A Low Area Fully Pipelined Implementation of JPEG on FPGA

Year 2018, Volume: 19 Issue: 3, 685 - 697, 01.09.2018

Abstract

This paper presents a low-area and high-throughput design and implementation of JPEG encoder on FPGA. The design consists of three main components: (1) 2-D DCT module, based on the row-column decomposition technique, (2) Quantization in zigzag ordering, based on look-up tables, and (3) Entropy coder, transforming the quantized DCT coefficients into JPEG words. All components are fully pipelined and optimized for FPGA resource utilization. The proposed implementation of JPEG encoder is able to encode 143 and 71 SDTV frames per second with 720x480 gray scale and color pixels per frame, respectively, on Xilinx Spartan 6 FPGA. Moreover, the proposed architecture is capable of encoding at least 53 and 26 HD Ready TV frames per second with 1280x720 gray scale and color pixels per frame, respectively, on this FPGA chip. Thus, the proposed JPEG encoder architecture is well-suited to various image and video compressing applications where performance and area are significantly important.

References

  • The International Telegraph and Telephone Consultative Committee (CCITT). Information Technology – Digital Compression and Coding of Continuous-Tone Still Images – Requirements and Guidelines. Rec. T.81, 1992.
  • Wallace GK. The JPEG still picture compression standard. IEEE T Consum Electr: 1992; 38: 18-34.
  • van Dyck W, Smodic R, Hufnagl H, Berndorfer T. High-speed JPEG coder implementation for a smart camera. J Real-Time Image Pr 2006; 1: 63-68.
  • Agostini LV, Silva IS, Bampi S. Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. Microprocess Microsy 2007; 31: 487-497.
  • Pradeepthi T, Ramesh AP. Pipelined architecture of 2D-DCT, quantization and zigzag process for JPEG image compression using VHDL. Int J VLSI Com (VLSICS) 2011; 2: 99-110.
  • Swarna KSV, Raju YDS. Implementation of soft processor based SOC for JPEG compression on FPGA. ICTACT J Microelectron 2015; 1: 1-7.
  • Kishore B, Kumar BKS, and Patil CR. FPGA based Simple and Fast JPEG Encryptor. J Real-Time Image Pr 2015; 10: 551-559.
  • Kaddachi ML, Soudani A, Lecuire V, Torki K, Makkaoui L, Moureaux J-M. Low power hardware-based image compression solution for wireless camera sensor networks. Comp Stand Inter 2012; 34: 14-23.
  • Kovac M, Ranganathan N. JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. Proc IEEE 1995; 83: 247-258.
  • Sun S-H, Lee S-J. A JPEG chip for image compression and decompression. J VLSI Signal Proc 2003; 35. 43-60.
  • Hsia S-C, Wang S-H. Shift-register-based data transposition for cost-effective discrete cosine transform. IEEE T VLSI Syst 2007; 15: 725-728.
  • Doğan A. An efficient low area implementation of 2-D DCT on FPGA. 9th International Conference on Electrical and Electronics Engineering (ELECO), 771-775.
  • Sanjeevannanavar S, Nagamani N. Efficient design and FPGA implementation of JPEG encoder using Verilog HDL. International Conference on Nanoscience, Engineering and Technology; 2011: 584-588.
  • Altera White Paper. 40-nm FPGAs: Architecture and Performance Comparison. 2008.
Year 2018, Volume: 19 Issue: 3, 685 - 697, 01.09.2018

Abstract

References

  • The International Telegraph and Telephone Consultative Committee (CCITT). Information Technology – Digital Compression and Coding of Continuous-Tone Still Images – Requirements and Guidelines. Rec. T.81, 1992.
  • Wallace GK. The JPEG still picture compression standard. IEEE T Consum Electr: 1992; 38: 18-34.
  • van Dyck W, Smodic R, Hufnagl H, Berndorfer T. High-speed JPEG coder implementation for a smart camera. J Real-Time Image Pr 2006; 1: 63-68.
  • Agostini LV, Silva IS, Bampi S. Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. Microprocess Microsy 2007; 31: 487-497.
  • Pradeepthi T, Ramesh AP. Pipelined architecture of 2D-DCT, quantization and zigzag process for JPEG image compression using VHDL. Int J VLSI Com (VLSICS) 2011; 2: 99-110.
  • Swarna KSV, Raju YDS. Implementation of soft processor based SOC for JPEG compression on FPGA. ICTACT J Microelectron 2015; 1: 1-7.
  • Kishore B, Kumar BKS, and Patil CR. FPGA based Simple and Fast JPEG Encryptor. J Real-Time Image Pr 2015; 10: 551-559.
  • Kaddachi ML, Soudani A, Lecuire V, Torki K, Makkaoui L, Moureaux J-M. Low power hardware-based image compression solution for wireless camera sensor networks. Comp Stand Inter 2012; 34: 14-23.
  • Kovac M, Ranganathan N. JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. Proc IEEE 1995; 83: 247-258.
  • Sun S-H, Lee S-J. A JPEG chip for image compression and decompression. J VLSI Signal Proc 2003; 35. 43-60.
  • Hsia S-C, Wang S-H. Shift-register-based data transposition for cost-effective discrete cosine transform. IEEE T VLSI Syst 2007; 15: 725-728.
  • Doğan A. An efficient low area implementation of 2-D DCT on FPGA. 9th International Conference on Electrical and Electronics Engineering (ELECO), 771-775.
  • Sanjeevannanavar S, Nagamani N. Efficient design and FPGA implementation of JPEG encoder using Verilog HDL. International Conference on Nanoscience, Engineering and Technology; 2011: 584-588.
  • Altera White Paper. 40-nm FPGAs: Architecture and Performance Comparison. 2008.
There are 14 citations in total.

Details

Journal Section Articles
Authors

Atakan Doğan This is me

İsmail San

Publication Date September 1, 2018
Published in Issue Year 2018 Volume: 19 Issue: 3

Cite

AMA Doğan A, San İ. A Low Area Fully Pipelined Implementation of JPEG on FPGA. Eskişehir Technical University Journal of Science and Technology A - Applied Sciences and Engineering. September 2018;19(3):685-697.