Research Article
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Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction

Year 2018, Volume 5, Issue 1, 44 - 55, 05.04.2018
https://doi.org/10.31593/ijeat.409405

Abstract

With the constant demand of automotive industries for embedded electronic devices in order to employ them in vehicles that needs constant monitoring and management of their energy systems, analog voltmeters stands out in this kind of application by their measurement efficiency and driver’s assistance. This electronic device is often used for variable’s controlling in fields where requires total measurement preciosion, such as: automotive ebedded systems,  process control, electrical machenary testing, electronic diagnosis and so on. The current work was designed to the development of an analog voltmeter PCB’s design layout based on DFMEA (Design Failure Mode and Effects Analysis) methodology, to avoid potential failures during design conception. The confection process of those PCB’s layouts begins with the analysis of two original circuits in AutoCAD, where the main problem verifyed was the alterations to be done in the circuits due the layer’s distribution scenario. This problem was solved through SMT components re-adjustment applying DFMEA methodology. In the application of this meyhodology, the percentage of  potential failures was about to 61% to the first circuit and 38% to the second circuit. This results idicates that the application of DFMEA in PCB’s design layout is highly efficient to detect, identify and classify the risk and severity of potential failures during the project development.              

Keywords- Vehicle electronics, embedded systems, DFMEA, PCB design, instrumentation, failure reduction

References

  • [1] F239 – Física Experimental III, “Instrumentos de medida elétrica,” Institúto de Física Gleb Wataghin – UNICAMP.
  • [2] D. K. Bonello, “Relatório de Estágio de Curso Técnico de Mecatrônica,” Colégio Politécnico Bento Quirino, 2011.
  • [3] A. Santana and M. Massarani, “Engenharia do valor associada ao DFMEA no desenvolvimento do produto,” Society of Automotive Engineers Inc, 2005.
  • [4] P. Theo and K. Case, “Failure modes and effects analysis through knowledge modelling,” Journal of Materials Processing Technology, pp.253-260.
  • [5] S.H. Teng and S.Y. Ho, “Failure mode and effects analysis,” International Journal of Quality & Reliability Management, vol. 13, pp.8-26, no.5.
  • [6] FMEA – Third Edition, “Potential failure mode and effects analysis,” DaimlerChrysler Corporation, Ford Motor Company, General Motors Corporation, 2001.
  • [7] FMEA Handbook, “Failure mode and effects analysis – version 4.1,” Ford Motor Company, 2004.
  • [8] Md. Imran Hossain Jony and Md. Moshiur Rahman, “Construction of microcontroller based digital voltmeter,” International Journal of Science and Research (IJSR), vol. 3, pp.1-4, no.1.
  • [9] S. Clodoaldo, “Aplicações com o circuito integrado LM3914,” Clube da Eletrônica, 2006. Avaliable at: http://www.clubedaeletronica.com.br.
  • [10] B. Newton C., “Produtos/componentes: código para resistores SMD,” Saber Eletrônica, 2008. Avaliable at: http://www.sabereletronica.com.br/secoes/leitura/658.
  • [11] B. Newton C., “Projetos/manutenção: retrabalho de componentes SMD,” Saber Eletrônica, 2008. Avaliable at: http://www.sabereletronica.com.br/secoes/leitura/1292.

Year 2018, Volume 5, Issue 1, 44 - 55, 05.04.2018
https://doi.org/10.31593/ijeat.409405

Abstract

References

  • [1] F239 – Física Experimental III, “Instrumentos de medida elétrica,” Institúto de Física Gleb Wataghin – UNICAMP.
  • [2] D. K. Bonello, “Relatório de Estágio de Curso Técnico de Mecatrônica,” Colégio Politécnico Bento Quirino, 2011.
  • [3] A. Santana and M. Massarani, “Engenharia do valor associada ao DFMEA no desenvolvimento do produto,” Society of Automotive Engineers Inc, 2005.
  • [4] P. Theo and K. Case, “Failure modes and effects analysis through knowledge modelling,” Journal of Materials Processing Technology, pp.253-260.
  • [5] S.H. Teng and S.Y. Ho, “Failure mode and effects analysis,” International Journal of Quality & Reliability Management, vol. 13, pp.8-26, no.5.
  • [6] FMEA – Third Edition, “Potential failure mode and effects analysis,” DaimlerChrysler Corporation, Ford Motor Company, General Motors Corporation, 2001.
  • [7] FMEA Handbook, “Failure mode and effects analysis – version 4.1,” Ford Motor Company, 2004.
  • [8] Md. Imran Hossain Jony and Md. Moshiur Rahman, “Construction of microcontroller based digital voltmeter,” International Journal of Science and Research (IJSR), vol. 3, pp.1-4, no.1.
  • [9] S. Clodoaldo, “Aplicações com o circuito integrado LM3914,” Clube da Eletrônica, 2006. Avaliable at: http://www.clubedaeletronica.com.br.
  • [10] B. Newton C., “Produtos/componentes: código para resistores SMD,” Saber Eletrônica, 2008. Avaliable at: http://www.sabereletronica.com.br/secoes/leitura/658.
  • [11] B. Newton C., “Projetos/manutenção: retrabalho de componentes SMD,” Saber Eletrônica, 2008. Avaliable at: http://www.sabereletronica.com.br/secoes/leitura/1292.

Details

Primary Language English
Subjects Engineering, Multidisciplinary
Journal Section Research Article
Authors

Daniel Bonello> (Primary Author)
University of Campinas
Brazil


Yuzo Iano This is me
University of Campinas
Brazil


Umberto Neto This is me
University of Campinas
Brazil

Publication Date April 5, 2018
Application Date March 25, 2018
Acceptance Date March 30, 2018
Published in Issue Year 2018, Volume 5, Issue 1

Cite

Bibtex @research article { ijeat409405, journal = {International Journal of Energy Applications and Technologies}, eissn = {2548-060X}, address = {editor.ijeat@gmail.com}, publisher = {İlker ÖRS}, year = {2018}, volume = {5}, number = {1}, pages = {44 - 55}, doi = {10.31593/ijeat.409405}, title = {Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction}, key = {cite}, author = {Bonello, Daniel and Iano, Yuzo and Neto, Umberto} }
APA Bonello, D. , Iano, Y. & Neto, U. (2018). Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction . International Journal of Energy Applications and Technologies , 5 (1) , 44-55 . DOI: 10.31593/ijeat.409405
MLA Bonello, D. , Iano, Y. , Neto, U. "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction" . International Journal of Energy Applications and Technologies 5 (2018 ): 44-55 <https://dergipark.org.tr/en/pub/ijeat/issue/36457/409405>
Chicago Bonello, D. , Iano, Y. , Neto, U. "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction". International Journal of Energy Applications and Technologies 5 (2018 ): 44-55
RIS TY - JOUR T1 - Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction AU - DanielBonello, YuzoIano, UmbertoNeto Y1 - 2018 PY - 2018 N1 - doi: 10.31593/ijeat.409405 DO - 10.31593/ijeat.409405 T2 - International Journal of Energy Applications and Technologies JF - Journal JO - JOR SP - 44 EP - 55 VL - 5 IS - 1 SN - -2548-060X M3 - doi: 10.31593/ijeat.409405 UR - https://doi.org/10.31593/ijeat.409405 Y2 - 2018 ER -
EndNote %0 International Journal of Energy Applications and Technologies Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction %A Daniel Bonello , Yuzo Iano , Umberto Neto %T Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction %D 2018 %J International Journal of Energy Applications and Technologies %P -2548-060X %V 5 %N 1 %R doi: 10.31593/ijeat.409405 %U 10.31593/ijeat.409405
ISNAD Bonello, Daniel , Iano, Yuzo , Neto, Umberto . "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction". International Journal of Energy Applications and Technologies 5 / 1 (April 2018): 44-55 . https://doi.org/10.31593/ijeat.409405
AMA Bonello D. , Iano Y. , Neto U. Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction. IJEAT. 2018; 5(1): 44-55.
Vancouver Bonello D. , Iano Y. , Neto U. Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction. International Journal of Energy Applications and Technologies. 2018; 5(1): 44-55.
IEEE D. Bonello , Y. Iano and U. Neto , "Proposal of an analog voltmeter PCB’s design layout based on DFMEA methodology for failure reduction", International Journal of Energy Applications and Technologies, vol. 5, no. 1, pp. 44-55, Apr. 2018, doi:10.31593/ijeat.409405