Stokastik Hesaplamada Çoklayıcıların Sınırı Üzerine

Abstract

On the Limit of Multiplexers in Stochastic Computing

Abstract

Stochastic computing (SC) is an approach used in today's re-emerging hardware environments. Known deterministic circuit elements are fed by binary sequences with probability, and the output sequence probability expresses a mathematical operation in terms of the probability of input sequences. Pulse trains expressed with probability values feed deterministic logic systems by expressing unipolar or bipolar encoding techniques, and an output pulse train with a probability value is obtained. This approach, which provides benefits in terms of complexity, low power, and durability especially for arithmetic operations, appears in applications with flexible fault tolerance such as computer vision. In this context, the multiplexer (MUX) logic system is used as a scaled adder; in other words, the sum of binary probabilistic sequences coming to the inputs of a MUX is seen at the output at the rate of a coefficient. In this study, the limits of the MUX structure within the scope of SC are underlined. With the MUX structures created with different hardware configurations, the architectures are investigated for performance.

Keywords

• bitstream processing
• multiplexers
• optimization
• scaled adder
• stochastic computing

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