Investigation of single phase reduced switch count asymmetric multilevel inverter using advanced pulse width modulation technique

Abstract

In this paper, a new topology for Multilevel Inverter (MLI) with reduced switch count is proposed with an asymmetric dc source configuration. This configuration is used to double the output voltage level in multilevel inverter based on switched dc sources, by adding two switches with dc sources. The increased number of levels in the output voltage reduces the filtering requirements. The working principle of the proposed asymmetric inverter is presented through the single phase fifteen level inverter. The harmonic contents of different modulation indices are examined. The performance analysis of the inverter is compared with trapezoidal and Sinusoidal Pulse Width Modulation (SPWM) in terms of Total Harmonic Distortion (THD), fundamental rms voltage (Vrms) and Crest Factor (CF). The simulation results for the same are evaluated using MATLAB/SIMULINK

Keywords

• Asymmetric; crest factor; multilevel inverter; pulse width modulation; total harmonic distortion

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