REALIZATION AND EXTENSIONS OF USER PROGRAMMABLE, SINGLE-LEVEL, DOUBLE-THRESHOLD GENERALIZED PERCEPTRON
Abstract
The implementation of a perceptron that can classify data separable by two parallel hyper-planes or equivalently
of a Single-Level TL-XOR gate is proposed using 10 MOS transistors and 2 capacitors. The functional subblock
decomposition of the Perceptron with two separating hyper-planes, its CMOS implementation explaining
the operation of each sub-block and simulation results, obtained using the SpectreS simulator and AMS 0.8mm
CMOS double-poly double-metal technology parameters are presented. A brief outline of the two level CTL
realization and its comparison with the new implementation are given as far as their transistor count,
programmability and total delay are concerned.
Key Words: Perceptron, Neural Networks, Threshold Logic, XOR Gate
Keywords
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Details
| Primary Language | English |
|---|---|
| Journal Section | Articles |
| Authors | |
| Publication Date | November 10, 2011 |
| Published in Issue | Year 2001 Volume: 1 Issue: 1 |
