Efficient Use of Application Specific CORDIC for Digital Demodulation in I/Q Receiver

Year 2013, Volume: 13 Issue: 1, 1581 - 1587, 02.09.2013

AMRITAKAR Mandal , RAJESH Mıshra

Abstract

Digital modalities of sine and cosine waves are gaining enormous attention in the field of vector rotated Digital Signal Processing (DSP) applications. COordinate Rotation DIgital Computer (CORDIC) algorithm has become very important and widely researched topic due to its simplicity to cater almost perfect digital sine and cosine waveforms during modulation and demodulation processes in various digital designs. In DSP applications, the quantization errors generated in CORDIC may propagate through subsequent modules ending up with reduced SNR of the system as a whole. In this paper, we have presented the design of a pipelined CORDIC architecture for detection of amplitude-  phase variations in a demodulator of FMCW radar. The angle approximation and rounding off error of CORDIC have been intensively studied for the determination of design parameters. An expression for overall quantization error is derived. The design of application specific CORDIC processor in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on FPGA is essential to the design of pipelined CORDIC and that can be achieved through the optimization in the number of micro rotations. Hardware synthesized result using Cadence design tools are presented.

Keywords

Digital Signal Processing (DSP), CORDIC, Pipelined Architecture, FMCW Radar, Quantization error

References

• J. E. Volder, "The CORDIC Trigonometric Computing Technique", IRE Transactions on Electronic Computing, vol. EC-8, pp. 330-334, Sept, 1959.
• Y. H. Hu, "CORDIC-Based VLSI Architectures for Digital Signal Processing", IEEE Signal Processing Magazine, vol. 9, no. 3, pp. 16-35, 1992.
• S. Aggarwal, P. K. Meher, K. Khare, "Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection", IEEE Transactions on VLSI System, vol. 20, no. 8, pp. 1542-1546, Aug, 2012.
• S. Ugazio, "Design of real time adaptive DPLLs for generic and variable Doppler frequency", in International Conference on Localization and GNNS (ICL-GNSS)”, pp. 169-174, Tampere, Jun, 2011.
• B. K. Kang, H. J. Kwon, B. K. Mheen, H. –J. Yoo and Y. H. Kim, "Nonlinearity Compensation Circuit for voltagecontrolled oscillator operating in linear frequency sweep Cells Leakage Power (nW) Dynamic Power (µW) Total Power (µW) 95 132 64 752 20 40 60 80 100 120 140 160 180 200 -1 P h a s e -A m p lit u d e V a ri a ti o n s Iterations 20 40 60 80 100 120 140 160 180 200 -1 -0.8 -0.6 -0.4 -0.2 D e m o d u la to r O u tp u t Iterations Types Instances Area Area % Sequentials 59 39784 0 Inverter 1 653 0.2 Logic 35 4002 8 Total 95 44438 0 E m b e d e d S ig n a l w it h P h a s e S h if t Iterations