System-Level Processing-Time Analysis of a NodeMCU-Based Asynchronous JK Flip-Flop Chain
Abstract
This study experimentally evaluates system-level processing and response times in a NodeMCU (ESP8266)-based software implementation of an asynchronous JK flip-flop (JK/FF) chain. Unlike field-programmable gate array (FPGA)-based remote-laboratory or hardware-level propagation-delay studies, the work focuses on timing overheads produced by a low-cost microcontroller software engine and its web-controlled measurement environment. Measurements were acquired separately for FF1-FF8 local stages and for the total FF1-FF8 asynchronous chain. For each group, 60 repetitions were recorded, with 30 measurements representing the 0→1 transition and 30 representing the 1→0 transition. Findings from 540 raw observations show that NodeMCU processing time is stable at approximately 13 μs in FF2-FF8 local measurements, increases to approximately 25 μs for FF1, and reaches approximately 73 μs in the total chain measurement. The total time variable exhibits wider millisecond-scale scattering because it also reflects browser, Wi-Fi/HTTP, and system-load effects. The results confirm that the measured quantity is not pure integrated-circuit propagation delay but a reproducible system-level timing response of a NodeMCU-based experimental engine.
Keywords
JK/FF, asynchronous chain, NodeMCU, system-level processing time, remote laboratory
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