VHDL İLE TAM GÖMÜLÜ BİR TETRİS OYUNU GERÇEKLEŞTİRMESİ

Öz

Bu çalışmada, bir FPGA geliştirme ve eğitim kiti üzerinde tam gömülü olarak çalışan bir Tetris oyun kodu gerçeklemesi yapılmıştır. Bunun için, FPGA kiti üzerinde bağımsız olarak çalışan, VHDL donanım tanımlama dilinde orijinal bir Tetris oyun kodu tasarlanmıştır. Bu tasarımın özgün yanı, şimdiye kadar bu konuda yapılmış birçok çalışmadan üstün olarak, tasarlanan kodun veri tutma işlemi için herhangi bir SRAM modülü kullanmamasıdır. Kodun yazımında karo-haritalamalı şema denilen, bir grup pikselin tamamını bir karo olarak tanımlayan bir haritalama kullanılmaktadır. Bu şema ile, ilgili karo içindeki piksellerin tamamı için 1-bit bilginin tutulması yeterli olduğundan kod tasarımı oldukça kolaylaşmakta ve aynı zamanda kodun hızlı çalışması sağlanmaktadır. Oyun kodu VHDL donanım tanımlama dilinde yazılmıştır. Sistem olarak Altera DE0 geliştirme ve eğitim kiti kullanılmıştır ancak yazılan kodda yalnız standart VHDL fonksiyonları kullanıldığından kod diğer FPGA kitleri üzerinde de çalışabilmektedir.

Anahtar Kelimeler

• FPGA Tetris,Gömülü sistem tasarımı,VHDL ile Tetris kodu,VHDL ile oyun kodu

A FULLY EMBEDDED TETRIS GAME APPLICATION IN VHDL

Abstract

In this paper, a Tetris game code which runs on an FPGA development and education board is synthesized. To this end, an original Tetris game code that works solely on the FPGA board is designed in VHDL hardware description language. The novelty of this design lies in the fact that the Tetris code does not use any SRAM modules for storage unlike other embedded Tetris implementations published to date. What is more, the code uses a tile-mapped scheme in which the code groups certain pixels as a tile. Thus, a 1-bit register is enough for the current value of all the pixels that fall in the tile which improves the speed of the code and simplifies the design procedure. The code is written using VHDL hardware description language. Though Altera DE0 development and education board is used for the implementation, thanks to the usage of only the standard VHDL functions, the code can run on any other FPGA boards.

Keywords

• FPGA Tetris,embedded system design,Tetris code in VHDL,game coding in VHDL

References

1. [1] HUTCHINGS, B., VILLASENOR, J., “The flexibility of configurable computing”. IEEE Signal Processing Magazine, 15, 67-84, 1998.
2. [2] BENEDETTI, A., PERONA, P., “Real-time 2-D feature detection on a reconfigurable computer”, Proc IEEE Comput Soc Conf Comput Vis Pattern Recognit,, 586-593, Santa Barbara, CA, USA, 1998.
3. [3] BOSI, B., BOIS, G., SAVARIA, Y., “Reconfigurable pipelined 2-D convolvers for fast digital signal processing”, IEEE Trans VLSI Syst., 7, 299-308, 1999.
4. [4] DIAZ, J., ROS, E., PELAYO, F., ORTIGOSA, E.M., MOTA, S., “FPGA-based real-time optical-flow system”, IEEE Trans Circuits Syst Video Technol, 16(2), 274-279, 2006.
5. [5] DOWNTON, A., CROOKES, D., “Parallel architectures for image processing”, J Electron Commun Eng, 10, 139-151, 1998.
6. [6] CROOKES, D., BENKRID, K., BOURIDANE, A., ALOTAIBI, K., BENKRID, A., “Design and implementation of a high level programming environment for FPGA-based image processing”, IEE Proceedings - Vision, Image and Signal Processing, 147(4), 377-384, 2000.
7. [7] UZUN, I.S., AMIRA, A., BOURIDANE, A., “FPGA implementations of fast Fourier transforms for real-time signal and image processing”, IEE Proceedings - Vision, Image and Signal Processing, 152(3), 283-296, 2005.
8. [8] JIN, S. et al, “FPGA Design and Implementation of a Real-Time Stereo Vision System”, IEEE Trans Circuits Syst Video Technol, 20(1), 15-26, 2010.

9. [9] YOUNG, J.W., MOYERS, J.C., LENOX, M., “FPGA based front-end electronics for a high resolution PET scanner”, IEEE Trans Nucl Sci, 47(4), 1676-1680, 2000.
10. [10] ANDORKO, I., CORCORAN, P.M., BIGIOI, P., “FPGA based stereo imaging system with applications in computer gaming”, International IEEE Consumer Electronics Society's Games Innovations Conference, 239-245, London, UK, 2009.
11. [11] LIU, K., YANG, Y., ZHU, Y., “Tetris game design based on the FPGA”, 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet), 2925-2928, 2012.
12. [12] WATANABE, T. et al, “An FPGA Connect6 Solver with a two-stage pipelined evaluation”, International Conference on Field-Programmable Technology (FPT), New Delhi, India, 2011.
13. [13] VIPIN, K., FAHMY, S.A., “A threat-based Connect6 implementation on FPGA”, International Conference on Field-Programmable Technology (FPT), New Delhi, India, 2011.
14. [14] FUJIMORI, T., WATANABE, M., “Full FPGA game machine”, 2016 IEEE International Conference on Consumer Electronics (ICCE), 431-432, Las Vegas, NV, USA, 2016.
15. [15] YOZA, T. et al, “FPGA Blokus Duo Solver using a massively parallel architecture”, 2013 International Conference on Field-Programmable Technology (FPT), 494-497, Kyoto, Japan, 2013.
16. [16] JAHANSHAHI, A., TARAM, M.K., ESKANDARI, N., “Blokus Duo game on FPGA”, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), 149-152, Tehran, Iran, 2013.
17. [17] FUJIMORI, T. et al, “FPGA Trax Solver based on a neural network design”, International Conference on Field Programmable Technology (FPT), 260-263, Queenstown, New Zealand, 2015.
18. [18] SZABÓ, R., GONTEAN, A., “Pong game on FPGA with CRT or LCD display and push button controls”, Federated Conference on Computer Science and Information Systems (FedCSIS), 729-734, Warsaw, Poland, 2014.
19. [19] ZHANG, G., XIE, M., “Design of visual based-FPGA Ping-Pang game with multi-models”, Second Pacific-Asia Conference on Circuits, Communications and System (PACCS), 31-34 Beijing, China, 2010.
20. [20] AZAR, Y., EPSTEIN, L., “On two dimensional packing”, Algorithm Theory – SWAT’96, Springer Berlin Heidelberg, 321-332. 1996.
21. [21] BREUKELAAR, R., DEMAINE, E., HOHENBERGER, S., HOOGEBOOM, H.J., KOSTERS, W.A., LIBEN-NOWELL, D. “Tetris is hard, even to approximate” J Comput Geom, 14, 41–68, 2004.
22. [22] CASAZZA, P.G., HEINECKE, A., KORNELSON, K., WANG, Y., ZHOU, Z., “Necessary and sufficient conditions to perform spectral Tetris”, Journal of Linear Algebra Applications, 438, 2239-2255, 2013.
23. [23] LANGENHOVEN, L., HEERDEN, W.S., ENGELBRECHT, A.P., “Swarm Tetris: applying particle swarm optimization to Tetris”, IEEE 2010 Congress on Evolutionary Computation, 1-8, Barcelona, Spain, 2010.
24. [24] HOLMES, E.A., JAMES, E.L., COODE-BATE, T., DEEPROSE, C., “Can playing the computer game Tetris reduce the build-up of flashbacks for trauma? A proposal from cognitive science”, J Plos One, 4, 4153, 2009.
25. [25] KENT, S., Ultimate History of Video Games, Three Rivers Press, New York, USA, 2001.
26. [26] TERASIC TECHNOLOGIES, Altera DE0 Development and Education Board User Manual, 2009.
27. [27] CHU, P.P., FPGA Prototyping by VHDL examples, John Wiley & Sons, New-Jersey, USA, 2008.
28. [28] PERRY, D.L., VHDL Programming by Example, McGraw-Hill, New York, USA, 2002.
29. [29] THOMAS, D.B., LUK, W., “FPGA-optimised uniform random number generators using LUTs and shift registers”, IEEE International Conference on Field Programmable Logic and Applications, 77-82, Milano, Italy, 2010.