Analysis and floor plan of multimedia design for the internet of things

Year 2025, Volume: 43 Issue: 1, 88 - 95, 28.02.2025

Ipseeta Nanda J. Midhunchakkaravarthy

Abstract

A platform for computation and communication is planned to support real time multimedia communication system architecture (MCSA) model for Internet of Things (IoT) application. In the current scenario, reducing the chip area plays an important role in chip design, where lower power consumption becomes significant consideration. We applied a Dynamic Partial Reconfiguration (DPR) to design a processor peripheral model, achieving area reduction and power efficiency. Furthermore, the Audio Communication System Architecture (ACSA) filter design plays an important role in multimedia systems, demonstrating greater feasibility in hardware implementation. The objective of the paper is to design flexible system for different application areas with the use of partial reconfiguration technique. This allows for enhanced application performance. Utilizing the Design Rule Check (DRC), we achieve high level design on Xilinx platform. In this work, we compared Audio Mutimedia Architecture ACSA design with and without DPR with area and power. Our work has given better performance with respect to area reduction and low power consumption with respected to existing methods.

Keywords

Audio Communication System Architecture, Design Rule Check, Dynamic Partial Reconfiguration, Internet of Things, Multimedia Communication System Architecture

References

• REFERENCES
• [1] Nanda I, Adhikari N. Application and performance of FPGA using partial reconfiguration with Xilinx PlanAhead. In 2017 IEEE Transportation Electrification Conference (ITEC-India) (pp. 1-4). IEEE, 2017. [CrossRef]
• [2] Siva Prasad B, Mallikarjuna Rao P, Madhav BTP. CPW fed T-stub and U-slot reconfigurable antenna for Wi-Fi and WLAN communication applications. J Adv Res Dyn Control Syst 2017;9(Suppl 14):2104–2116.
• [3] Nanda I, Ali SM. Implementation and execution of math partial reconfiguration region and LED dealing with Xilinx PlanAhead. Int J Adv Electron Electr Eng 2015;4:1–3. [CrossRef]
• [4] Balaji S, Khan H, Janga Reddy M, Gurunadha Babu M. Authentication frameworks for enhancing security in biometric systems. Int J Mech Eng Technol 2017;8:1073–1080.
• [5] Kao C. Benefits of partial reconfiguration. Xcell J 2005;55:65–67.
• [6] Murali Krishna B, Madhumati GL, Khan H. Dynamically evolvable hardware-software co-design based crypto system through partial reconfiguration. J Theoretic Appl Inform Technol 2017;95:2159–2169.
• [7] Nanda I, Pujari S, Panda CS. Implementation of math PRR and LED processing using Xilinx PlanAhead. In 2015 International Conference on Computing Communication Control and Automation (pp. 955-958). IEEE, 2015. [CrossRef]
• [8] Peesapati R, Anumandla KK, Sabat SL. Performance evaluation of floating point Differential Evolution hardware accelerator on FPGA. IEEE Region 10 Annual International Conference, Proceedings/ TENCON, pp. (3173–3178), 2017. [CrossRef]
• [9] Hübner M, Becker J. Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. In Proceedings of the 19th annual symposium on Integrated circuits and systems design (pp. 1–4), 2016. [CrossRef]
• [10] Saleem Akram P, Madhav BTP, Jeevana Sravya G, Sudhakar V, Lakshmi Sirisha G, Mounika C, et al. Design and analysis of square shaped serrated patch antenna for ultra-wideband applications with single rejection band. Int J Eng Technol 2018;7:525–529. [CrossRef]
• [11] Bhandari SU, Subbaraman S, Pujari S, Mahajan R. Internal dynamic partial reconfiguration for real time signal processing on FPGA. Indian J Sci Technol 2010;3:365–368. [CrossRef]
• [12] Madhav BTP, Sai Dheeraj G, Raghavarapu SS. Design of a CPW-fed monopole antenna for ultrawide band based iot and medical applications. Int J Pharm Res 2018;10:74–79. [CrossRef]
• [13] Lopez-Buedo S, Garrido J, Boemo EI. Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems. IEEE Trans Compon Packag Technol 2010;25:561–566. [CrossRef]
• [14] Madhav BTP, Venkateswara Rao T, Tirunagari A. Design of 4-element printed array antenna for ultra-wideband applications. Int J Microw Opt Technol 2018;13:8–17.
• [15] Eto E. (2007). Difference-based partial reconfiguration. XAPP290 (v2. 0) December, 3.
• [16] Srikanth Reddy P, Satyanarayana P, Sai Krishna G, Divya K. Hardware implementation of variable digital filter using constant coefficient multiplier for SDR applications. Adv Intell Syst Comput 2018;668:495–502. [CrossRef]
• [17] Two Flows for Partial Reconfiguration: Module Based or Difference Based Xilinx,, XAPP290 (v1.2) September 9, 2004.
• [18] Partial Reconfiguration Design with Planahead 9.2 by Brian Jackson Ver1.1, August 2007.
• [19] Cheerla S, Venkata Ratnam D, Teja Sri KS, Sahithi PS, Sowdamini G. Neural network based indoor localization using Wi-Fi received signal strength. J Adv Res Dynam Control Syst 2018;10:374–379.
• [20] Media Presentation. Using the PlanAhead 9.2 for Partial reconfiguration flow Xilinx, Brain Jackson.
• [21] Timing S, Device X. Xilinx ISE 8 software manuals and help-PDF collection, 2015.
• [22] Nanda I, Adhikari N. Application and performance of FPGA using partial reconfiguration with Xilinx PlanAhead. In 2017 IEEE Transportation Electrification Conference (ITEC-India) (pp. 1-4). IEEE, 2017. [CrossRef]
• [23] XPS HWICAP (v1.00.a), DS586, Xilinx, November 05, 2007.
• [24] Nanda I, Adhikari N. Study and design of reconfigurable processor peripherals using Xilinx tools. J Electron Des Technol 2018;9:17–23.
• [25] Biradar V, Reddy BM, Anumandla KK. DM3730 Processor Hardware Debugging on Linux Platform. 2018 4th International Conference for Convergence in Technology, I2CT 2018. [CrossRef]
• [26] Kishore KH, Prasad BKV, Teja YMS, Akhila D, Sai KN, Kumar PS. Design and comparative analysis of inexact speculative adder and multiplier. Int J Eng Technol 2018;7(Suppl 8):413–418. [CrossRef]
• [27] Zalke JB, Pandey SK. Dynamic partial reconfigurable embedded system to achieve hardware flexibility using 8051 based RTOS on Xilinx FPGA. In 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies (pp. 684-686). IEEE, 2009. [CrossRef]
• [28] Chaitanya NK, Varadarajan S. Load distribution using multipath-routing in wired packet networks: A comparative study. Perspect Sci 2016;8:234–236. [CrossRef]
• [29] Fernando X, Lăzăroiu G. Spectrum sensing, clustering algorithms, and energy-harvesting technology for cognitive-radio-based internet-of-things networks. Sensors 2023;23:779. [CrossRef]
• [30] Kulakli A, Arikan CL. Research trends of the ınternet of things in relation to business model innovation: results from co-word and content analyses. Future Internet 2023;15:81. [CrossRef]
• [31] Wang Y, Su Z, Guo S, Dai M, Luan TH, Liu Y. A survey on digital twins: architecture, enabling technologies, security and privacy, and future prospects. IEEE Access 2023;10:1–27. [CrossRef]
• [32] Azzaz MS, Kaibou R, Madani B, Arzazi M, Dahmane K. FPGA Implementation of Real-Time Video Watermarking Prototype Using PL-PS Embedded Processor Over Network Communication. In 2023 International Conference on Networking and Advanced Systems (ICNAS) (pp. 1-6). IEEE, 2023. [CrossRef]
• [33] Faizan M, Intzes I, Cretu I, Meng H. Implementation of deep learning models on an SoC-FPGA device for real-time music genre classification. Technologies 2023;11:91. [CrossRef]
• [34] Mani V, Ghonge MM, Chaitanya NK, Pal O, Sharma M, Mohan S, Ahmadian A. A new blockchain and fog computing model for blood pressure medical sensor data storage. Comput Electric Eng 2022;102:108202. [CrossRef]
• [35] Popoff M, Michon R, Risset T, Cochard P, Letz S, Orlarey Y, et al. Audio DSP to FPGA Compilation: The Syfala Toolchain Approach (Doctoral dissertation). Lyon: Univ Lyon, INSA Lyon, Inria, CITI, Grame, Emeraude; 2023. [CrossRef]
• [36] Al-Dulaimi MAA, Wahhab HA, Amer AA. Design and implementation of communication Digital FIR filter for audio signals on the FPGA platform. J Commun 2023;18:89–96. [CrossRef]
• [37] Ding B, Huang J, Wang J, Xu Q, Chen S, Kang Y. Task modules partitioning, scheduling and floorplanning for partially dynamically reconfigurable systems with heterogeneous resources. ACM Trans Design Autom Electron Syst 2023;28:1–26. [CrossRef]