Comparative Analysis of Analog and FPGA Realizations Based on Matsuda Method for Fractional Order Integral Operator

Öz

Realization of fractional order (FO) transfer functions is essential for real-time applications such as communication systems, video, and digital signal processing. In general, in both implementation methods, the FO transfer function including FO integral and derivative operators is transformed to an integer order approximate transfer function by one of the approximation methods such as Oustaloup, Matsuda, CFE, MSBL, etc. Then, the integer order approximate transfer function can be implemented using analog circuit elements such as opamps, resistors, capacitors, or digitally with field-programmable gate arrays (FPGA). In this study, integer order approximate continuous time transfer function obtained for FO integral operator by Matsuda’s approximation method is converted to a discrete time function, and that function is digitally implemented by FPGA with Xilinx System Generator. The results obtained are analyzed in comparison with analog circuit implementation results presented in a former study. The study emphasizes the growing importance of fractional calculus in providing accurate models for real-world systems and the challenges posed by the long memory effect in digital implementations. Simulation and experimental results, including sinusoidal waveform, step response and impulse response analysis, reveal the pros and cons of FPGA implementation. Considering these issues, conclusions are made on the effectiveness, efficiency and potential of the FPGA implementation for real-time applications in control systems and signal processing.

Anahtar Kelimeler

• Fractional Order Integral
• Matsuda’s Method
• Field Programmable Gate Array (FPGA)
• Digital Circuit Implementation.

Kaynakça

1. [1] M. Koseoglu, F. N. Deniz, B. B. Alagoz, A. Yuce, and N. Tan, “An experimental analog circuit realization of Matsuda’s approximate fractional-order integral operators for industrial electronics,” Eng. Res. Express, vol. 3, no. 4, p. 045041, Dec. 2021, doi: 10.1088/2631-8695/ac3e11.
2. [2] A. M. Hassanein, A. H. Madian, A. G. G. Radwan, and L. A. Said, “On the Design Flow of the Fractional-Order Analog Filters Between FPAA Implementation and Circuit Realization,” IEEE Access, vol. 11, pp. 29199–29214, 2023, doi: 10.1109/ACCESS.2023.3260093.
3. [3] J. Nako, C. Psychalinos, and A. S. Elwakil, “A 1 + α Order Generalized Butterworth Filter Structure and Its Field Programmable Analog Array Implementation,” Electronics, vol. 12, no. 5, p. 1225, Mar. 2023, doi: 10.3390/electronics12051225.
4. [4] M. A. George, A. S. Elwakil, A. Allagui, and C. Psychalinos, “Design of Complex-Order PI/PID Speed Controllers and its FPAA Realization,” IEEE Access, vol. 11, pp. 118606–118614, 2023, doi: 10.1109/ACCESS.2023.3326446.
5. [5] A. Ali, K. Bingi, R. Ibrahim, P. A. M. Devan, and K. B. Devika, “A review on FPGA implementation of fractional-order systems and PID controllers,” AEU - Int. J. Electron. Commun., vol. 177, p. 155218, Apr. 2024, doi: 10.1016/j.aeue.2024.155218.
6. [6] C. X. Jiang, J. E. Carletta, and T. T. Hartley, “Implementation of Fractional-order Operators on Field Programmable Gate Arrays,” in Advances in Fractional Calculus: Theoretical Developments and Applications in Physics and Engineering, J. Sabatier, O. P. Agrawal, and J. A. T. Machado, Eds., Dordrecht: Springer Netherlands, 2007, pp. 333–346. doi: 10.1007/978-1-4020-6042-7_23.
7. [7] W. Wolf, FPGA-based system design. Pearson education, 2004.
8. [8] U. Meyer-Baese and U. Meyer-Baese, Digital signal processing with field programmable gate arrays, vol. 65. Springer, 2007.

9. [9] M. Koseoglu, “Time response optimal rational approximation: Improvement of time responses of MSBL based approximate fractional order derivative operators by using gradient descent optimization,” Eng. Sci. Technol. Int. J., vol. 35, p. 101167, Nov. 2022, doi: 10.1016/j.jestch.2022.101167.
10. [10] F. N. Deniz, B. B. Alagoz, N. Tan, and M. Koseoglu, “Revisiting four approximation methods for fractional order transfer function implementations: Stability preservation, time and frequency response matching analyses,” Annu. Rev. Control, vol. 49, pp. 239–257, 2020, doi: 10.1016/j.arcontrol.2020.03.003.
11. [11] G. F. Franklin, J. D. Powell, and M. L. Workman, Digital control of dynamic systems, vol. 3. Addison-wesley Menlo Park, 1998.
12. [12] “Matlab Documentation ‘c2d,’” c2d. [Online]. Available: https://www.mathworks.com/help/control/ref/dynamicsystem.c2d.html?s_tid=doc_ta
13. [13] K. Ogata, Discrete-time control systems. Prentice-Hall, Inc., 1995.
14. [14] J. G. Proakis, Digital signal processing: principles, algorithms, and applications, 4/E. Pearson Education India, 2007.
15. [15] “Xilinx System Generator for DSP Getting Started Guide.” AMD. Accessed: Aug. 16, 2024. [Online]. Available: https://docs.amd.com/v/u/en-US/sysgen_gs
16. [16] A. Sharma and T. K. Rawat, “Design and FPGA implementation of lattice wave fractional order digital differentiator,” Microelectron. J., vol. 88, pp. 67–78, Jun. 2019, doi: 10.1016/j.mejo.2019.04.013.
17. [17] D. Datta and H. S. Dutta, “High performance IIR filter implementation on FPGA,” J. Electr. Syst. Inf. Technol., vol. 8, no. 1, p. 2, Dec. 2021, doi: 10.1186/s43067-020-00025-4.
18. [18] V. Dhillon, S. Nair, A. Pabarekar, M. Kumbhare, K. Thakur, and R. Krishnan, “Implementation of FIR Digital Filter on FPGA,” in 2021 4th Biennial International Conference on Nascent Technologies in Engineering (ICNTE), NaviMumbai, India: IEEE, Jan. 2021, pp. 1–5. doi: 10.1109/ICNTE51185.2021.9487744.
19. [19] H. V. Dixit and D. V. Gupta, “IIR filters using Xilinx System Generator for FPGA implementation,” Int. J. Eng. Res. Appl., vol. 2, no. 5, pp. 303–307, 2012.
20. [20] P. Paz and M. Garrido, “Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices,” J. Signal Process. Syst., vol. 95, no. 4, pp. 543–550, Apr. 2023, doi: 10.1007/s11265-023-01867-7.
21. [21] P. Kwiatkowski, “Digital-to-time converter for test equipment implemented using FPGA DSP blocks,” Measurement, vol. 177, p. 109267, Jun. 2021, doi: 10.1016/j.measurement.2021.109267.