Comparative Analysis of Analog and FPGA Realizations Based on Matsuda Method for Fractional Order Integral Operator

Abstract

Realization of fractional order (FO) transfer functions is essential for real-time applications such as communication systems, video, and digital signal processing. In general, in both implementation methods, the FO transfer function including FO integral and derivative operators is transformed to an integer order approximate transfer function by one of the approximation methods such as Oustaloup, Matsuda, CFE, MSBL, etc. Then, the integer order approximate transfer function can be implemented using analog circuit elements such as opamps, resistors, capacitors, or digitally with field-programmable gate arrays (FPGA). In this study, integer order approximate continuous time transfer function obtained for FO integral operator by Matsuda’s approximation method is converted to a discrete time function, and that function is digitally implemented by FPGA with Xilinx System Generator. The results obtained are analyzed in comparison with analog circuit implementation results presented in a former study. The study emphasizes the growing importance of fractional calculus in providing accurate models for real-world systems and the challenges posed by the long memory effect in digital implementations. Simulation and experimental results, including sinusoidal waveform, step response and impulse response analysis, reveal the pros and cons of FPGA implementation. Considering these issues, conclusions are made on the effectiveness, efficiency and potential of the FPGA implementation for real-time applications in control systems and signal processing.

Keywords

• Fractional Order Integral
• Matsuda’s Method
• Field Programmable Gate Array (FPGA)
• Digital Circuit Implementation.

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