Design of TCAM Architecture for Low Power and High Performance Applications

Abstract

Content Addressable Memory (CAM) is a special memory used in search engines for numerous applications, especially in network routers for packet forwarding. The CAM operation begins with pre-charging followed by evaluating the match-lines (MLs) for searching the data in the stored memory. CAM stores unique words in their array of cells such that only one word is matched for a given search word. ML associated with matched word retains its state and the remaining MLs drain their charge. Ternary content addressable memory (TCAM) is a fast lookup hardware device used for high-speed packet forwarding. However, significant power consumption and high cost limits its versatility and popularity. In this paper, a design has been made for TCAM architecture with pre-charge controller. The pre-charge controller helps in predicting the mismatched MLs during pre-charge phase. This prediction happens at an early stage and helps in terminating the pre-charging of the line. This assures the design of TCAM which consumes low power and also improves the performance. The proposed early predict 8 × 8 TCAM architecture simulations were performed in 45nm technology node using Cadence Virtuoso. The proposed TCAM design exhibits 16.6% reduction in power, 24.7% decrement in delay and 37.1% minimization in energy metric than basic TCAM NOR. 

Keywords

• Delay,Early-predict,Match-line,Search-line,Pre-charge,Energy metric,Power

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