Reduction of Output Impedance of Buck Converter with Genetic Algorithm

Abstract

This paper introduces a technique to reduce the output impedance in the PWM buck converters with voltage-mode control (VMC) without requiring low Equivalent Series Resistance (ESR) output capacitors. Proposed technique uses the infinity norm ( ) to convert the problem into an optimization problem. Obtained optimization problem is solved with the aid of Genetic Algorithm (GA). The proposed technique is applied to a sample buck converter operating in Continuous Conduction Mode (CCM). Simulink simulation is used to test the suggested method. Simulation results showed a considerable decrease in the low frequency region of output impedance. Such a decrease in output impedance is very desired for low voltage high current loads like computer CPU’s.

Keywords

• DC-DC converters
• load transients
• output impedance of buck converter
• State Space Averaging (SSA).

References

1. [1] E. Joard, J. Villarejo, F. Soto, and J. Muro, “Effect of the Output Impedance in Multiphase Active Clamp Buck Converters,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3231-3238, Sep. 2008.
2. [2] D. Goder and W. R. Pelletier, “V2 architecture provides ultra-fast transient response in switch mode power supplies,” in Proc. HFPC, 1996, pp. 16-23.
3. [3] J. Xu, X. Cao, and Q. Luo, “The effects of control techniques on the transient response of switching DC-DC converters,” in Proc. IEEE PEDS, 1999, pp. 794-796
4. [4] P. Wong, F. C. Lee, X. Zhou, and J. Chen, “VRM transient study and output filter design for future processors,” in Proc. IEEE IECON, 1998, pp. 410-415.
5. [5] D. Briggs, R. Martinez, R. Miftakhutdinov, and D. Skelton, “A fast, efficient synchronous buck controller for microprocessor power supplies,” in Proc. HFPC, 1998, pp. 170-176.
6. [6] B. Arbetter and D. Maksimovic, “DC-DC converter with fast transient response and high efficiency for low-voltage microprocessor loads,” in Proc. IEEE APEC, 1998, pp. 156-162.
7. [7] R. Miftakhutdinov, “Analysis of synchronous buck converter with hysteretic controller at high slew-rate load current transients,” in Proc. HPFC, 1999, pp. 55-69.
8. [8] C. J. Mehas, K. D. Coonley, and C. R. Sullivan, “Converter and inductor design for fast response microprocessor power delivery,” in Proc. IEEE PESC, 2000, pp. 1621-1626.

9. [9] L. D. Varga and N. A. Losic, “Synthesis of zero-impedance converter,” IEEE Trans. on Power Electronics, vol. 7, no. 1, Jan 1992.
10. [10] R. Redl and N. Sokal, “Near-optimum dynamic regulation of dc-dc converters using feed forward of output current and input voltage with current-mode control,” IEEE Trans. on Power Electronics, vol. PE-1, no. 3, Jul 1986
11. [11] J. Steenis, “Details on compensating voltage mode buck regulators,” Power Management Design Line, September 4, 2006.
12. [12] W.H. Lei, T.K. Man, “A general approach for optimizing dynamic response for buck converter,” ON Semiconductor, Apr. 2004.
13. [13] T. Hagerty, “Voltage-mode control and compensation: Intricacies for buck regulators,” Electronics Design, Strategy, News (edn.com), June 30, 2008.
14. [14] L. Zhao, “Closed-loop compensation design of a synchronous switching charger using bq2472x/3x,” Texas Instruments application report, September 2006.
15. [15] “A handy method to obtain satisfactory response of buck converter,” Analog Integrations Corporation, application note AN021, October 2001.
16. [16] “Loop compensation of voltage-mode buck converters,” Sipex Corporation Technical Note, October 11, 2006.
17. [17] D. Mattingly, “Designing stable compensation networks for single phase voltage mode buck regulators,” Intersil Corporation Technical Note TB417.1, December 2003.
18. [18] Asadi F, Eguchi K. Dynamics and control of DC-DC converters, San Rafael: Morgan and Claypool; 2018. p. 89-145. [19] Suntio T. Dynamic profile of switched mode converter: modeling, analysis and control. New Jersy: John Wiley & Sons. 2009. p. 17-37. [20] Gu D, Petkov P, Konstantinov M. Robust Control Design with MATLAB.Springer. 2013. p. 9-11.