Cryogenic DC Characteristics of Low Threshold Voltage (VTH) n-channel MOSFETs

Abstract

Cryogenic electronics has grown in its widespread use for various technological applications. Particularly, CMOS devices and circuits are more frequently used in such systems due to their dominance in the electronics industry. At cryogenic temperatures, characteristics of CMOS devices vary, which should be characterized with measurements. In this paper, the changes in the electronic behavior of a low threshold voltage (V_TH) n-channel MOSFET (nMOSFET) are captured experimentally. The results are then compared with the measurements of a regular nMOSFET having the same channel width and length. It is shown that although the V_TH increase of both transistors is at the same amount, this value corresponds to a more significant percentage of the nominal threshold voltage for the low V_TH nMOSFET. 

Keywords

• Cryogenic electronics,threshold voltage,low threshold voltage transistors

Project Number

215E080

References

1. Shafique, A., Yazici, M., Kayahan, H., Ceylan, O., Gurbuz, Y., “Cryogenic Measurements of a Digital Pixel Readout Integrated Circuit for LWIR,” Proc. SPIE 9451, Infrared Technology & Applications, XLI, 94510Y, 1 – 6, 2015.
2. Ceylan, O., Kayahan, H., Yazici, M., Baran, M.B., Gurbuz, Y., “Design and Realization of 144 x 7 TDI ROIC with Hybrid Integrated Test Structure”, Proc. SPIE 8353, Infrared Technology & Applications, XXXVIII, 83531Q, 1 – 12, 2012.
3. Cressler, J.D. “Silicon-Germanium as an Enabling Technology for Extreme Environment Electronics,” IEEE Transactions Device and Materials Reliability (TDMR), 10, 4, 437 – 448, 2010.
4. Woods, B. O., Mantooth H. A., Cressler, J. D., “SiGe HBT Compact Modeling for Extreme Temperatures,” ISDRS, College Park, Maryland, ABD, 1 – 2, 2007.
5. Kabaoğlu, A., and Yelten, M. B., “A cryogenic modeling methodology of MOSFET IV characteristics in BSIM3”, In IEEE 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 1-4, 2017.
6. Ladd, T.D., Jelezko, F., Laflamme, R., Nakamura, Y., Monroe, C., O’Brien, J.L., “Quantum Computers”, Nature, vol. 464, 45 – 53, 2010.
7. Homulle, H., Visser, S., Patra, B., Ferrari, G., Prati, E., Almudéver, C.G., Bertels, K., Sebastiano, F., Charbon, E., 2016. “CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer” Proceedings of the ACM International Conference on Computing Frontiers (CF '16). ACM, New York, NY, ABD, 282-287.
8. Ware, F., Gopalakrishnan, L., Linstadt, E., McKee, S. A., Vogelsang, T., “Do Superconducting Processors Really Need Cryogenic Memories? The Case for Cold DRAM”, In ACM Proceedings of the International Symposium on Memory Systems, pp. 183-188, October 2017.

9. Tannu, S. S., Carmean, D. M., & Qureshi, M. K., “Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study,” In Proceedings of the ACM International Symposium on Memory Systems, pp. 189-195, October 2017.
10. Streetman, B. and Banerjee, S., 2016, “Solid State Electronic Devices,” Pearson Education, Global 7th edition, Essex, İngiltere.
11. Kabaoğlu, A., Solmaz, N. Ş., İlik, S., Uzun Y., and Yelten, M. B. "Statistical MOSFET Modeling Methodology for Cryogenic Conditions," in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 66-72, Jan. 2019.