Resource Efficient Implementation of Keccak, Skein & JH Algorithms on Reconfigurable Platform

Year 2016, Volume: 13 Issue: 1 , - , 01.05.2016

Dur-e-shahwar Kundi Arshad Aziz Kashif Latif

https://izlik.org/JA59ZA55JP

Abstract

In this work, we present a compact hardware implementation of cryptographic hash algorithms;
[Keccak, Skein & JH] on Field Programmable Gate Array (FPGA) by using an efficient primitive level
programming approach. All the logic is not only mapped onto Look-Up-Table (LUT) but also effectively
utilizes FPGAs internal dedicated logical resource, such as Fast Carry Chain logic with MUXCY and
XORCY to reduce overall hardware resources. This approach results in the usage of a minimized chip area
with a good balance between resources and speed for selected hash algorithms. All the implementation has
been done on the latest Xilinx FPGAs and their results comparisons are presented in the form of chip area
consumption, throughput and throughput per area with previous up-to-date implementations. The results
show a substantial improvement as compared to all the previously reported works.

Keywords

Cryptographic Hash Functions , FPGA , JH , Keccak , Skein

References

• [1] X. L. Xiaoyun Wang, D. Feng, H. Yu., Collisions for hash functions MD4, MD5, HAVAL-128 and RIPEMD. Cryptology ePrint Archive, Report 2004/199, (2004), 1-4. URL: http://eprint.iacr.org/2004/199
• [2] M. Szydlo, SHA-1 collisions can be found in 263 operations, CryptoBytes Technical Newsletter, (2005).
• [3] M. Stevens, Fast collision attack on MD5. Cryptology ePrint Archive, Report 2006/104, (2006), 1-13, URL: http://eprint.iacr.org/2006/104.pdf
• [4] K. Aoki, J. Guo, K. Matusiewicz, Y. Sasaki, L. Wang, Preimages for Step-Reduced SHA2, In: Advances in Cryptology ASIACRYPT, Lecture Notes in Computer Science, 5912, Springer Berlin /Heidelberg, (2009), 578-597.
• [5] National Institute of Standards and Technology (NIST). SHA-3 Winner announcement, (2012), URL: http://www.nist.gov/itl/csd/sha-100212.cfm
• [6] I. F., Alshaikhli, M. A., Alahmad, K. Munthir, Comparison and Analysis Study of SHA-3 Finalists, International Conference on Advanced Computer Science Applications and Technologies, (2012), 366-371.
• [7] J. Daemen, V. Rijmen, The Design of Rijndael – AES Advanced Encryption Standard. Springer-Verlag Inc., New York USA (2002)
• [8] Xilinx: 7 Series FPGAs Configurable Logic Block user guide. v1.7, Technical report (2014), URL: http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
• [9] L. Henzen, P. Gendotti, P. Guillet, E. Pargaetzi, M. Zoller, F. K. Gurkaynak, Developing a hardware evaluation method for SHA-3 candidates, Proc. Cryptographic Hardware and Embedded Systems, (2010), 248-263.
• [10] S. Tillich, M. Feldhofer, M. Kirschbaum, T. Plos, J.-M. Schmidt, and A. Szekely, HighSpeed Hardware Implementations of Blake, Blue Midnight Wish, Cubehash, ECHO, Fugue, Grøstl, Hamsi, JH, Keccak, Luffa, Shabal, Shavite-3, SIMD, and Skein, Cryptology ePrint Archive, Report 2009/510, (2009), URL: http://eprint.iacr.org/2009/510.pdf
• [11] F. K. Gürkaynak, K. Gaj, B. Muheim, E. Homsirikamol, C. Keller, M. Rogawski, H. Kaeslin, J. -P. Kaps, Lessons Learned from Designing a 65nm ASIC for Evaluating Third Round SHA-3 Candidates, 3rd SHA-3 Candidate Conference, (2012), 1-21.
• [12] B. Jungk, M. Stöttinger: Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK. 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip), (2013), 1-8.
• [13] S. Kerckof, F. Durvaux, N. Charvillon, F. Regazzoni, G. Meurice, F. Standaert, Compact FPGA Implementations of the Five SHA-3 Finalists, CARDIS 2011, LNCS, Springer Berlin Heidelberg, 7079, (2011), 217-233.
• [14] B. Jungk, Compact Implementations of Grøstl, JH and Skein for FPGAs, ECRYPT II Hash Workshop 2011, (2011), 1-15.
• [15] X. Guo, S. Huang, L. Nazhandali, P. Schaumont, On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings, Cryptology ePrint Archive, Report 2010/536, (2010), URL:http://eprint.iacr.org/2010/536.pdf
• [16] The SHA-3 Zoo Hardware Implementations, URL: http://ehash.iaik.tugraz.at/wiki/SHA3_Hardware_Implementations
• [17] B. Baldwin, N. Hanley, M. Hamilton, L. Lu, A. Byrne, M. Neill and W. P. Marnane, FPGA Implementations of the Round Two SHA-3 Candidates, 2nd SHA-3 Candidate Conference, (2010), 1-18.
• [18] S. Matsuo, M. Knezevic, P. Schaumont, I. Verbauwhede, A. Satoh, K. Sakiyama, K. Ota, How Can We Conduct Fair and Consistent Hardware Evaluation for SHA-3 Candidate? 2nd SHA-3 Candidate Conference, (2010), 1-15.
• [19] K. Gaj, E. Homsirikamol, M. Rogawski, R. Shahid, M. U. Sharif, Comprehensive evaluation of High Speed and medium speed implementations of five SHA-3 finalist using Xilinx and Altera FPGAs, 3rd SHA-3 Candidate Conference, (2012).
• [20] R. Shahid, M. U. Sharif, M. Rogawski, K. Gaj, Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates, IEEE International Conference on Field-Programmable Technology, (2011), 1-9.
• [21] E. Homsirikamol, M. Rogawski, K. Gaj, Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs, Cryptographic Hardware and Embedded Systems, LNCS, Springer Berlin Heidelberg, 6917, (2011), 491-506.
• [22] E. Homsirikamol, M. Rogawski, K. Gaj, Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architectures in Xilinx and Altera FPGAs, ECRYPT II Hash Workshop 2011, (2011), 1-15.
• [23] J. Strömbergson, Implementation of the Keccak Hash Function in FPGA Devices, (2008), 1-4, URL: http://www.strombergson.com/files/Keccak_in_FPGAs.pdf
• [24] A. Akin, A. Aysu, O. C. Ulusel, E. Savas, Efficient Hardware Implementations of High Throughput SHA-3 Candidates Keccak, Luffa and Blue Midnight Wish for Single- and Multi-Message Hashing, 2nd SHA-3 Candidate Conference, (2011).
• [25] M. Long, Implementing Skein Hash function on Xilinx Virtex-5 FPGA platform, (2009), URL: http://www.skein-hash.info/sites/default/files/skein_fpga.pdf
• [26] S. Tillich, Hardware implementation of the SHA-3 candidate Skein, Cryptology ePrint Archive, Report 2009/159, (2009), URL: http://www.eprint.iacr.org/2009/159.pdf
• [27] G. Bertoni, J. Daemen, M. Peeters, G. V. Assche, The Keccak SHA-3 Submission version 3, (2011), 1-14, URL: http://keccak.noekeon.org/Keccak-submission-3.pdf
• [28] K. Latif, A. Aziz, A. Mahboob, Optimal Utilization of Available Reconfigurable Hardware Resources, Elsevier Computer and Electrical Engineering, 37(6), (2011), 1043-1057.
• [29] N. Ferguson, S. Lucks, B. Schneier, D. Whiting, M. Bellare, T. Kohno, J. Callas, J. Walker, The Skein Hash Function Family Version 1.3, (2010), 1-100, URL: http://www.skein-hash.info/sites/default/files/skein1.3.pdf
• [30] H. Wu., The Hash Function JH, (2011), 1-54, URL: http://www3.ntu.edu.sg/home/wuhj/research/jh/jh_round3.pdf