Resource Efficient Implementation of Keccak, Skein & JH Algorithms on Reconfigurable Platform

Year 2016, Volume: 13 Issue: 1, - , 01.05.2016

Dur-e-shahwar Kundi Arshad Aziz Kashif Latif

Abstract

In this work, we present a compact hardware implementation of cryptographic hash algorithms;
[Keccak, Skein & JH] on Field Programmable Gate Array (FPGA) by using an efficient primitive level
programming approach. All the logic is not only mapped onto Look-Up-Table (LUT) but also effectively
utilizes FPGAs internal dedicated logical resource, such as Fast Carry Chain logic with MUXCY and
XORCY to reduce overall hardware resources. This approach results in the usage of a minimized chip area
with a good balance between resources and speed for selected hash algorithms. All the implementation has
been done on the latest Xilinx FPGAs and their results comparisons are presented in the form of chip area
consumption, throughput and throughput per area with previous up-to-date implementations. The results
show a substantial improvement as compared to all the previously reported works.

Keywords

Cryptographic Hash Functions, FPGA, JH, Keccak, Skein

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