Gelişmiş Şifreleme Standardı (AES) Algoritmasının Yan-Kanal Saldırılarına Dayanıklı ve Enerji Verimliliği Yüksek Paralel ASIC Uygulaması

Abstract

Şifreleme, giderek birbirine bağlanan bir dünyada her zamankinden daha önemli hale gelmektedir. Gelişmiş Şifreleme Standardı (AES), matematiksel özellikleri sayesinde 20 yıldan fazla bir süre sonra hala güvenli kabul edilmektedir. Ancak yan kanal saldırıları (SCA), uygunsuz AES uygulamalarını tehdit etmektedir. Bu çalışmada farklı AES uygulamaları tanıtılmakta ve bunların güç Yan-Kanal Saldırısı’na (SCA), spesifik olarak Korelasyon Güç Analizi (CPA) saldırısı, karşı dirençleri gösterildi. Enerji verimliliği açısından, yan-kanal saldırısına karşı yapılan eklemeler nedeniyle güç tüketiminde meydana gelen artış, yazmaç düzeyindeki organizasyonlar ve çip akışı bazlı optimizasyonlar ile minimuma indirildi. Farklı AES uygulamaları oluşturuldu ve Cadence ASIC akışı (TSMC 65 nm LP teknolojisi) aracılığıyla işlendi. Yan-Kanal Saldırısı direnci, RTL'den GDSII'ye çip akışından sonra elde edilen gerçekçi güç tüketimi değerleri üzerinde çalışan ChipWhisperer platformu kullanılarak değerlendirildi. Sonuçlar, AES turlarının boru hattına yerleştirilmesinin ve açılmasının (unroll), enerji verimliliğinde minimum azalma karşılığında Yan-Kanal Saldırısı direncini arttırdığını göstermektedir. Önerilen uygulamalar farklı Yan-Kanal Saldırısı savunma önlemleriyle kullanılmaya uygundur.

Keywords

• Gelişmiş Şifreleme Standardı (AES) ASIC Uygulaması
• Donanım Güvenliği
• Dijital CMOS Tasarımı
• Yan-Kanal Saldırıları
• Korelasyon Güç Analizi (CPA)
• ChipWhisperer

An Energy-efficient Parallel ASIC Implementation of Advanced Encryption Standard (AES) Algorithm Robust against Side-channel Attacks

Abstract

Encryption becomes more crucial than ever in an increasingly interconnected world. Advanced Encryption Standard (AES) is still considered secure after more than 20 years thanks to its mathematical properties. However, side-channel attacks (SCA) threaten improper AES implementations. In this paper, different AES implementations are introduced, and their resistances against power SCA, namely Correlation Power Analysis (CPA) attack, are shown. For energy efficiency, the increase in power consumption due to the extras added for countering SCA was minimized by register-level organizations and process-related optimizations. Different AES implementations were constructed and processed through Cadence ASIC flow (TSMC 65 nm LP technology). SCA resistance was evaluated using the ChipWhisperer platform operating on realistic power consumption values obtained after RTL-to-GDSII flow. The results demonstrate that pipelining and unrolling the AES rounds increase the SCA resistance at the expense of a minimal reduction in energy efficiency. The proposed implementations are suitable for use with different side-channel attack countermeasures.

Keywords

• ASIC Implementation of Advanced Encryption Standard (AES)
• Hardware Security
• Digital CMOS Design
• Side-Channel Attacks
• Correlation Power Analysis (CPA)
• ChipWhisperer

Supporting Institution

TUBITAK

Ethical Statement

This article does not require ethics committee approval. This article has no conflicts of interest with any individual or institution.

Thanks

This research was conducted while the first author was an employee of TUBITAK. We thank TUBITAK BILGEM for allowing us to use the ASIC tools required to complete this work.

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