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A 4 Bit Time to Digital Converter Design Based on Flash Structure

Year 2019, , 52 - 62, 30.03.2019
https://doi.org/10.29130/dubited.463124

Abstract

This paper presents a 4-bit Time to Digital Converter (T/D) design using the Tanner Tools Pro with 0.25μm CMOS model library. The proposed T/D converter consists of delay block, comparator block, dynamic latch, multiplexer block, PLA-ROM. The proposed T/D converter consumes 126.3mW from 0-3.3V supply. Resolution of the proposed T/D converter is about 1.31ns. The INL and DNL of the designed 4 Bit T/D Converter are (-0.28/0.29)LSB and (-0.2/+0.6)LSB, respectively.

References

  • [1] D. Cahyadi, R. Kusumah, G. Kumara, A. H. Salman and A. F. Mas'ud, “Design and Implementation of SAR ADC for Timeto-Digital Converter Application”, IEEE Region 10 Conference TENCON 2015, 2015, ss.:1- 5.
  • [2] M. Rezvanyvardom, E. Farshıdı, “A Novel Cyclic Time-to-Digital Converter Based on Triple-Slope Interpolation and Time Amplification”, Radioengineering, vol. 24, no. 3, pp 800-807, 2015.
  • [3] M. Rezvanyvardom, T.G. Nejad, E. Farshidi, “A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy”, Information Processing in Agriculture, vol. 1, no.2, pp. 124-130, 2014.
  • [4] B. Markovic, S. Tisa, F. A. Villa, A. Tosi and F. Zappa, “A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 557-569, March 2013.
  • [5] K. Kim, W. Yu, S. Cho, “A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register”, IEEE Journal of Solid-State Circuits, vol. 49, no..4, pp. 1007-1016, 2014.
  • [6] S. Henzler, “Time-to-digital converters”, Springer Science & Business Media, 2010.
  • [7] Y. Cao, P. Leroux, W. De Cock, M. Steyaert, “A 1.7 mW 11b 1–1–1 MASH ΔΣ time-to-digital converter”, IEEE International Solid-State Circuits Conference, 2011, pp. 480-482.
  • [8] C.M. Lai, Y.C. Chen, P.C. Huang, “Time-domain analog-to-digital converters with domino delay lines”, International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 2013, pp 1-4.
  • [9] P.M. Levine, G. W. Roberts, “A high-resolutıon flash time-to-digital converter and calibration scheme”, International Test Conference(IEEE Cat. No.04CH37586), 2004, pp 1148-1157.
  • [10] K.S. Kim, Y.H. Kim, W.S. Yu, S.H. Cho, “A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier”, IEEE Journal of Solid-State Circuits, vol. 48, no.4, pp 1009-1017, 2013.
  • [11] R. Jiang, C. Li, M. Yang, H. Kobayashi, Y. Ozawa, N. Tsukiji, M. Hirano, R. Shiota, K. Hatayama, “Successive approximation time-to-digital converter with vernier-level resolution”, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 2016, pp 1-6,.
  • [12] J.D.A. van den Broek, “Design and Implementation of an Analog-to-Time-to-Digital converter”, Master’s Thesis, pp 1-76, 2012.
  • [13] A. Tangel, O. Aytar, F. Tekin, A. Çelebi, “Yüksek hızlı CMOS analog-sayısal dönüştürücülerin VLSI tasarımı ve imalatı”, TÜBİTAK EEEAG Proje 102E001, pp. 1-59, 2005.
  • [14] B. Razavi, B.A. Wooley,“Design Techniques for High- Speed, High Resolution Comparators”, IEEE Journal of Solid- State Circuits, no. 12, pp. 1916–1926, 1992.
  • [15] S. Babayan-Mashhadi, R. Lotfi, “Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, no. 2, pp. 343–352, 2014.
  • [16] K. Sahin, O. Aytar, A. Tangel, “5 Bit 2.5 Gs/s paralel (Flash) analog sayısal dönüştürücü tasarımı”, Elektrik Elektronik Bilgisayar Sempozyumu, Elazığ, Türkiye, 2011, pp. 125–130,.
  • [17] INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs), Maxim Integrated Techical Documents, (20.08.2018), https://www.maximintegrated.com/en/app-notes/index.mvp/id/283.
  • [18] Understanding Data Converters Application Report, Texas Instruments, (20.08.2018), http://www.ti.com/lit/an/slaa013/slaa013.pdf.

4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı

Year 2019, , 52 - 62, 30.03.2019
https://doi.org/10.29130/dubited.463124

Abstract

Yapılan
bu çalışmada, Tanner Tools Pro devre tasarım programında 0.25μm CMOS model
kütüphanesi kullanılarak flash tabanlı 4 bit Zaman-Sayısal Dönüştürücü(Z /S)(Time-to-Digital
Converter(TDC)) yapısı önerilmiştir. Tasarlanan zaman-sayısal dönüştürücü
devresi; zaman geciktirme birimi, karşılaştırıcı, dinamik tutucu, çoğullayıcı
devre ve PLA-ROM devre bloklarından oluşmaktadır. Önerilen bu Z/S dönüştürücü
tasarımı 3.3V besleme gerilimi altında toplam 126.3mW güç harcamaktadır.
Tasarlanan Z/S dönüştürücünün çözünürlüğü 1.31ns olup, INL değeri
(-0.28/0.29)LSB ve DNL değeri (-0.2/+0.6) LSB olarak bulunmuştur

References

  • [1] D. Cahyadi, R. Kusumah, G. Kumara, A. H. Salman and A. F. Mas'ud, “Design and Implementation of SAR ADC for Timeto-Digital Converter Application”, IEEE Region 10 Conference TENCON 2015, 2015, ss.:1- 5.
  • [2] M. Rezvanyvardom, E. Farshıdı, “A Novel Cyclic Time-to-Digital Converter Based on Triple-Slope Interpolation and Time Amplification”, Radioengineering, vol. 24, no. 3, pp 800-807, 2015.
  • [3] M. Rezvanyvardom, T.G. Nejad, E. Farshidi, “A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy”, Information Processing in Agriculture, vol. 1, no.2, pp. 124-130, 2014.
  • [4] B. Markovic, S. Tisa, F. A. Villa, A. Tosi and F. Zappa, “A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 557-569, March 2013.
  • [5] K. Kim, W. Yu, S. Cho, “A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register”, IEEE Journal of Solid-State Circuits, vol. 49, no..4, pp. 1007-1016, 2014.
  • [6] S. Henzler, “Time-to-digital converters”, Springer Science & Business Media, 2010.
  • [7] Y. Cao, P. Leroux, W. De Cock, M. Steyaert, “A 1.7 mW 11b 1–1–1 MASH ΔΣ time-to-digital converter”, IEEE International Solid-State Circuits Conference, 2011, pp. 480-482.
  • [8] C.M. Lai, Y.C. Chen, P.C. Huang, “Time-domain analog-to-digital converters with domino delay lines”, International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 2013, pp 1-4.
  • [9] P.M. Levine, G. W. Roberts, “A high-resolutıon flash time-to-digital converter and calibration scheme”, International Test Conference(IEEE Cat. No.04CH37586), 2004, pp 1148-1157.
  • [10] K.S. Kim, Y.H. Kim, W.S. Yu, S.H. Cho, “A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier”, IEEE Journal of Solid-State Circuits, vol. 48, no.4, pp 1009-1017, 2013.
  • [11] R. Jiang, C. Li, M. Yang, H. Kobayashi, Y. Ozawa, N. Tsukiji, M. Hirano, R. Shiota, K. Hatayama, “Successive approximation time-to-digital converter with vernier-level resolution”, IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 2016, pp 1-6,.
  • [12] J.D.A. van den Broek, “Design and Implementation of an Analog-to-Time-to-Digital converter”, Master’s Thesis, pp 1-76, 2012.
  • [13] A. Tangel, O. Aytar, F. Tekin, A. Çelebi, “Yüksek hızlı CMOS analog-sayısal dönüştürücülerin VLSI tasarımı ve imalatı”, TÜBİTAK EEEAG Proje 102E001, pp. 1-59, 2005.
  • [14] B. Razavi, B.A. Wooley,“Design Techniques for High- Speed, High Resolution Comparators”, IEEE Journal of Solid- State Circuits, no. 12, pp. 1916–1926, 1992.
  • [15] S. Babayan-Mashhadi, R. Lotfi, “Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, no. 2, pp. 343–352, 2014.
  • [16] K. Sahin, O. Aytar, A. Tangel, “5 Bit 2.5 Gs/s paralel (Flash) analog sayısal dönüştürücü tasarımı”, Elektrik Elektronik Bilgisayar Sempozyumu, Elazığ, Türkiye, 2011, pp. 125–130,.
  • [17] INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs), Maxim Integrated Techical Documents, (20.08.2018), https://www.maximintegrated.com/en/app-notes/index.mvp/id/283.
  • [18] Understanding Data Converters Application Report, Texas Instruments, (20.08.2018), http://www.ti.com/lit/an/slaa013/slaa013.pdf.
There are 18 citations in total.

Details

Primary Language Turkish
Subjects Engineering
Journal Section Articles
Authors

Yasin Talay This is me

Oktay Aytar 0000-0001-7664-103X

Publication Date March 30, 2019
Published in Issue Year 2019

Cite

APA Talay, Y., & Aytar, O. (2019). 4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı. Duzce University Journal of Science and Technology, 7(2), 52-62. https://doi.org/10.29130/dubited.463124
AMA Talay Y, Aytar O. 4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı. DÜBİTED. March 2019;7(2):52-62. doi:10.29130/dubited.463124
Chicago Talay, Yasin, and Oktay Aytar. “4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı”. Duzce University Journal of Science and Technology 7, no. 2 (March 2019): 52-62. https://doi.org/10.29130/dubited.463124.
EndNote Talay Y, Aytar O (March 1, 2019) 4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı. Duzce University Journal of Science and Technology 7 2 52–62.
IEEE Y. Talay and O. Aytar, “4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı”, DÜBİTED, vol. 7, no. 2, pp. 52–62, 2019, doi: 10.29130/dubited.463124.
ISNAD Talay, Yasin - Aytar, Oktay. “4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı”. Duzce University Journal of Science and Technology 7/2 (March 2019), 52-62. https://doi.org/10.29130/dubited.463124.
JAMA Talay Y, Aytar O. 4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı. DÜBİTED. 2019;7:52–62.
MLA Talay, Yasin and Oktay Aytar. “4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı”. Duzce University Journal of Science and Technology, vol. 7, no. 2, 2019, pp. 52-62, doi:10.29130/dubited.463124.
Vancouver Talay Y, Aytar O. 4 Bit Flash Tabanlı Zaman Sayısal Dönüştürücü Tasarımı. DÜBİTED. 2019;7(2):52-6.